At one point, the following code was added to the part of the kernel that brings the system out of a low-power state:

        ;
        ; Invalidate the processor cache so that any stray gamma
        ; rays (I'm serious) that may have flipped cache bits
        ; while in S1 will be ignored.
        ;
        ; Honestly.  The processor manufacturer asked for this.
        ; I'm serious.
        ;
         invd

I’m not sure what the thinking here is. I mean, if the cache might have been zapped by a stray gamma ray, then couldn’t RAM have been zapped by a stray gamma ray, too? Or is processor cache more susceptible to gamma rays than RAM? The person who wrote the comment seems to share my incredulity.

Less than three weeks later, the INVD instruction was commented out. But the comment block remains.

In case we decide to resume trying to deal with gamma rays corrupting the the processor cache, I guess.

Bonus chatter: One of my colleagues wasn’t part of this specific change, but recalled that these sorts of strange-sounding requests were not uncommon, especially for early processor steppings. The workaround was removed once the problem was fixed in microcode or in a later processor stepping.