Announcing HLSL Shader Model 6.6
After months of development and refinement in collaboration with hardware vendors and software developers, we are pleased to announce the availability of Shader Model 6.6! Shader Model 6.6 empowers shader authors with new tools for greater flexibility to make existing shaders faster
and more versatile as well as to devise all new techniques.
To give Shader Model 6.6 a try, developers will need a few tools. To compile shaders using Shader Model 6.6, you need the latest DirectX Shader Compiler release. To run those compiled shaders, you’ll need the DirectX 12 Agility SDK and the corresponding graphics driver.
New Atomic Operations
Shader Model 6.6 introduces 64-bit integer and limited bitwise floating-point atomic operations by overloading the Interlocked* functions and methods used on group shared memory, raw buffer, and typed (RWBuffer/RWTexture) resources.
See the Shader Model 6.6 Atomic Operations specification
for more details.
Shader Model 6.6 introduces the ability to create resources from descriptors by directly indexing into the CBV_SRV_UAV (resource view) heap or the Sampler heap. No root signature descriptor table mapping is required for this resource creation method, but new global root signature flags are used to indicate the use of each heap from the shader.
A short example:
Texture2D<float4> myTexture = ResourceDescriptorHeap[texIdx];
float4 result = myTexture.Sample(SamplerDescriptorHeap[sampIdx], coord);
Helper Lane Detection
IsHelperLane() is a new intrinsic introduced in Shader Model 6.6 that returns true if the current lane is a helper lane. Helper lanes are nonvisible pixels that are executed only to provide quad neighbor information to gradient operations. They can arise by being discarded or by sharing a quad with rendered pixels, but not contributing to any primitive. In a pixel shader, IsHelperLane() returns false for all visible pixels. In all other shader stages, it returns false for all lanes since they have no helper lanes.
IsHelperLane() is supported in previous shader models via emulation.
When using wave intrinsics in pixel shaders, you can end up with undefined results for certain values in helper lanes because helper lanes do not participate. This can lead to problems like undefined screen-space derivatives or unintentional infinite loops (hangs) when depending on results from wave intrinsics. In the past, we attempted to guard against this problem by disallowing potentially problematic operations from being dependent on the result of wave intrinsics. However, this could be too strict, or even miss some dependencies. This guard has been changed into a warning, but leaves the shader author without an explicit way to write safe code in that area of interaction. IsHelperLane provides a way for the shader to explicitly vary behavior on helper lanes to guard against potential problems. For instance, by explicitly excluding helper lanes from entering a loop which depends on a wave intrinsic for its exit condition.
Shader Model 6.6 introduces support for quad-based derivative operations to compute and optionally mesh and amplification shaders. We define how threads are mapped to 2×2 quads in these stages and specifically which operations are newly available.
See the Derivative Operations in Compute, Mesh and Amplification Shaders specification
for more details.
Pack and Unpack Intrinsics
A new set of intrinsics are being added to HLSL for processing of packed 8-bit data such as colors. New packed datatype are also added to HLSL’s front end to symbolize a vector of packed 8-bit values.
See the Shader Model 6.6 Pack/Unpack Intrinsics specification
for more details.
Shader Model 6.6 introduces a new option that allows the shader author to specify a wave size that the compute shader is compatible with. Such shaders will only be run with the specified wave size.
Raytracing Payload Access Qualifiers
Shader models 6.6 adds payload access qualifiers (PAQs) to the ray payload structure. PAQs are annotations which describe the read and write semantics of a payload field, that is, which shader stages read or write a given field. The added semantic information can help implementations reduce register pressure and can avoid spilling of payload state to memory. This incentivizes the use of the narrowest-possible qualifiers for each payload field.
See the new Payload Access Qualifiers section
of the raytracing specification for more details.