Today, we are pleased to announce that Shader Model 6.9 and other features have been officially released with Agility SDK 1.619 and complementary DXC 1.9.2602.16. Many of these features have been in preview status since 2025. Simultaneously, we are releasing a handful of new preview features in a separate preview runtime: Agility SDK 1.719-preview.
Overview
AgilitySDK 1.619 exposes the following features. There’s more detail further below, including download and driver links.
- Shader Model 6.9 (via DXC 1.9.2602.16):
- Long Vector
- 16 bit float Specials
- 16-bit and 64-bit shader op and wave ops are now required features
- HLSL exposure of the following in DXR 1.2:
- DXR 1.2:
- Opacity Micromaps (Released earlier, with small SM 6.9 portion lit up now)
- Shader Execution Reordering
- D3D Customer-Requested Features:
- Revised Resource View Creation APIs
- Periodic Trim Notifications
- Increased Dispatch Grid Limit
- CPU Timeline Query Resolves
AgilitySDK 1.719-preview exposes the features in 1.619 in addition to the following preview D3D features, with more detail further below.
- Enhanced Barriers update: Fence Barriers
- VPblit 3DLUT
- Extension Mechanism
Downloads
- AgilitySDK 1.619 and 1.719-preview: https://devblogs.microsoft.com/directx/directx12agility/
- DXC 1.9.2602.17: https://github.com/microsoft/DirectXShaderCompiler/releases
Hardware Support
| IHV | Driver Link(s) |
| AMD | AMD Software: Adrenalin Edition 26.2.1, AMD Software: AgilitySDK Developer Preview Edition 25.30.21.01 |
| Intel | Intel® Arcâ„¢ Graphics – Windows |
| NVIDIA | Download The Official NVIDIA Drivers | NVIDIA or the NVIDIA App, which handles automatic driver updates. Driver version 595 and newer. |
See Appendix > Feature Support for the full table of each feature’s supported hardware.
AgilitySDKÂ 1.619 Features
Long Vector
The ability to load, store, and perform elementwise operations on HLSL vectors longer than 4 elements and up to 1024.  Required as part of Shader Model 6.9. Spec: https://github.com/microsoft/hlsl-specs/blob/main/proposals/0026-hlsl-long-vector-type.md
In addition to the above spec, check out this overview: https://devblogs.microsoft.com/directx/hlsl-native-and-long-vectors/. This mentions Cooperative Vector benefitting from Long Vectors; however, note that Cooperative Vector has been deprecated in favor of a future design unifying matrix-matrix and vector-matrix operations, coming in Shader Model 6.10. See this earlier blog: https://devblogs.microsoft.com/directx/shader-model-6-9-and-the-future-of-cooperative-vector/
16 bit float Specials
HLSL IsNan(), IsInf(), IsFinite() now also support 16 bit floats. Also newly added IsNormal(), including 16 bit support.
Spec: https://github.com/microsoft/hlsl-specs/blob/main/proposals/0038-16bit-isspecialfloat.md
Previously optional features required in SM 6.9
Spec:Â https://github.com/microsoft/hlsl-specs/blob/main/proposals/0044-sm69-required-features.md
D3D12_FEATURE_DATA_D3D12_OPTIONS4.Native16BitShaderOpsSupportedD3D12_FEATURE_DATA_D3D12_OPTIONS1.WaveOpsD3D12_FEATURE_DATA_D3D12_OPTIONS1.Int64ShaderOps
DXR 1.2
Opacity Micromaps
Opacity Micromaps (OMMs) enable hardware to handle alpha tested geometry more efficiently than relying only on costly AnyHit shader invocations. The overall feature shipped previously and just the small HLSL portion is coming out of preview.Â
Blog with more details for OMM overall: https://devblogs.microsoft.com/directx/d3d12-opacity-micromaps/
Shader Execution Reordering
Shader Execution Reordering (SER) enables application shader code to inform hardware on how to find coherency across rays so they can be sorted for better parallel execution.Â
This feature is coming out of preview now.  The addition since preview is that apps can query if a device actually reorders.
See details in the device support section of this blog which covers SER overall: https://devblogs.microsoft.com/directx/shader-execution-reordering/
D3D Customer-Requested Features
Revised Resource View Creation APIs
As GPU architectures have evolved, the original D3D12 view‑creation model has shown limitations, especially around buffer access patterns, descriptor management, and alignment rules. Revised View Creation modernizes this area of the API in response to multiple customer requests.
Previously, buffers views were limited to being measured in elements. With this change, they can now be measured using byte offsets and sizes too. In addition, variants of view creation have been added that return HRESULT rather than void to allow for programmatic error handling, as opposed to relying on the debug layer validation and dealing with a device removal.
Spec: https://github.com/microsoft/DirectX-Specs/blob/master/d3d/D3D12RevisedCreateViews.md
Periodic Trim Notifications
Kernel-level trim notifications are now available through D3D12 runtime interfaces, enabling applications to receive notifications when the system should trim residency. No new driver support is required for this feature.
Spec: https://github.com/microsoft/DirectX-Specs/blob/master/d3d/D3D12_PeriodicTrimNotifications.md
Increased 1D Dispatch Limit
Increases the maximum 1-Dimensional Dispatch/DispatchMesh size (Currently 65535) to a device specific value which is much larger for most recent hardware.
D3D12_FEATURE_DATA_D3D12_OPTIONS22.Max1DDispatchSizeD3D12_FEATURE_DATA_D3D12_OPTIONS22.Max1DDispatchMeshSize
Spec: https://github.com/microsoft/DirectX-Specs/blob/master/d3d/D3D12IncreasedDispatchDimension.md
CPU Timeline Query Resolves
A new kind of Query Heap which can be resolved on the CPU timeline, avoiding unnecessary GPU work and overhead. Introduces ID3D12Device15::CreateQueryHeap1 along with ID3D12Device15::ResolveQueryData.
Spec: https://github.com/microsoft/DirectX-Specs/blob/master/d3d/D3D12CpuTimelineQueryResolution.md
AgilitySDK 1.719-preview Features
The following preview features are available in 1.719-preview: https://devblogs.microsoft.com/directx/directx12agility/
Enhanced Barriers update: Fence Barriers
Fence Barriers expand on Enhanced Barriers to provide support for signaling and waiting on fences during command buffer execution. This provides more flexibility to synchronize between more distant dependencies in the command stream and allows for real-time dependencies between the GPU timeline and CPU timeline.
See this separate blog for full details: https://devblogs.microsoft.com/directx/fence-barriers-fine-grained-gpu-synchronization-in-direct3d-12/
VPblit 3DLUT
The D3D12 VPBlit 3DLUT API enables access to dedicated video processing hardware for tone mapping operations that combine CSC, 1D LUT, and 3D LUT stages. While equivalent functionality can be achieved using D3D12 shaders on the 3D engine, exposing the video processing 3DLUT path through this API allows drivers and hardware to execute these operations more efficiently. This offloads tone mapping work from the 3D GPU engine and, in some scenarios, can reduce power consumption by leveraging the video processing engine. For detailed information, please refer to the spec document.
Driver support is available as follows:
- Intel: Intel Coreâ„¢ Ultra processor family Lunar Lake and Panther Lake platforms have support for this feature when using driver version 32.0.101.8531 or higher. Developers can also refer to Intel’s D3D12 VPBlit 3DLUT sample app.
- AMD: AMD’s driver will support the 3DLUT API beginning with the Feb 2026 Developer Preview release (25.30) on Radeon™ RX 7000 series graphics cards and Ryzen™ AI 300/400 series processors with integrated graphics.
- Other IHVs: Please contact your developer relations representative for specifics.
Extension Mechanism
The D3D12 Extensions API enables GPU hardware vendors (IHVs) and software developers (ISVs) to collaborate on new experimental graphics features. By providing a structured extension mechanism within the D3D12 ecosystem, vendors can expose experimental or vendor-specific capabilities immediately, gather real-world feedback, and iterate rapidly—dramatically shortening the time it takes to bring features into the core API.
The core interface, ID3D12Extension, derives from ID3D12DeviceChild and integrates seamlessly with D3D12’s object model. Extensions communicate through D3D12_EXTENSION_ARGUMENTS (flexible input/output buffers) and can hook into standard operations like resource creation via ID3D12DeviceApiExtensions.
PIX
PIX supports all retail and preview features released here. See this PIX blog: https://devblogs.microsoft.com/pix/pix-2602-25
Appendix
Feature Support
Using the latest drivers linked in Overview > Hardware Support:
| AMD | Intel | NVIDIA | |
| Long Vector | AMD Radeon™ RX 9000 series | Intel® Arc™ B-Series Graphics | All RTX hardware |
| 16 bit float Specials | AMD Radeon™ RX 9000 series | Intel® Arc™ B-Series Graphics |  All RTX hardware |
| Opacity Micromaps (OMM) | – | – | Â All RTX hardware. Hardware-accelerated on RTX 4xxx+ GPUs, software-emulated on older. |
| Shader Execution Reordering (SER) | AMD Radeonâ„¢ RX 9000 series supports API but doesn’t reorder. | Intel® Arcâ„¢ B-Series Graphics support API and do reordering. | RTX 4xxx+ GPUs support API and do reordering. |
| Revised Resource View Creation APIs | AMD Radeon™ RX 7000 and 9000 series | Intel® Arc™ B-Series Graphics |  All RTX hardware |
| Periodic Trim Notifications | – | Intel® Arcâ„¢ B-Series Graphics |  All RTX hardware |
| Increased Dispatch Grid Limit | AMD Radeon™ RX 7000 and 9000 series. UINT_MAX compute, 64k mesh. | Intel® Arc™ B-Series Graphics. Existing 64k limit, to increase in future drivers. | All RTX hardware. Existing 64k limit, to increase in future drivers. |
| CPU Timeline Query Resolves | AMD Radeon™ RX 7000 and 9000 series | Intel® Arc™ B-Series Graphics |  All RTX hardware |
| Fence Barriers (preview) | AMD Radeon™ RX 7000 and 9000 series | Intel® Arc™ B-Series Graphics | Contact your developer relations representative for in-development driver access. |
| VPblit 3DLUT (preview) | AMD Radeonâ„¢ RX 7000 series graphics cards and Ryzenâ„¢ AI 300/400 series processors with integrated graphics | Intel Coreâ„¢ Ultra processor family Lunar Lake and Panther Lake platforms | Contact your developer relations representative for specifics. |
0 comments
Be the first to start the discussion.