Introducing Fence Barriers
We are excited to share the preview release of Fence Barriers (Tier-1), a new capability now available in AgilitySDK 1.719-preview (https://devblogs.microsoft.com/directx/directx12agility/). Fence Barriers expand on Enhanced Barriers to provide support for signaling and waiting on fences during command buffer execution. This provides more flexibility to synchronize between more distant dependencies in the command stream and allows for real-time dependencies between the GPU timeline and CPU timeline.
This preview exposes Tier-1 Fence Barriers, which supports:
SignalBarrier– Signals a fence when a barrier has completed execution.WaitBarrier– Waits for one or more fences to be signaled before issuing a dependent barrier.- Tier-1 supports only Command List Scoped fences signaled earlier in the same command buffer execution context.
- Provides a cleaner, more expressive option over split barriers.
Looking ahead, Tier-2 (in-development) will expand WaitBarrier support to include fences signaled by the CPU or other GPU queues, supporting more sophisticated CPU/GPU and cross-queue rendering scenarios.
See the updated EnhancedBarriers spec for details on FenceBarriers.
Split Barrier Replacement Example
// Create a command list scoped fence
ComPtr<ID3D12Fence> pScopedFence;
pDevice->CreateFence(0, D3D12_FENCE_FLAG_ALLOW_COMMAND_LIST_BARRIERS,
IID_PPV_ARGS(&pScopedFence));
// Initiate split barrier - begins layout transition without blocking
pCommandList->SignalBarrier(pScopedFence, 1, /* barrier group */);
// Do other independent work here...
// Complete split barrier - wait for layout transition to finish
pCommandList->WaitBarrier(pScopedFence, 1, /* barrier group */);
// Now safe to use the resource
Cross-Queue Synchronization
Tier-1 supports using SignalBarrier to improve work coordination across GPU queues. A compute queue can signal a fence after completing barrier operations, and a direct queue can then use traditional queue-level Wait (not WaitBarrier) or poll the fence from the CPU. WaitBarrier in Tier-1 only works with Command List Scoped Fences—Tier-2 will add WaitBarrier support for cross-queue scenarios.
When synchronizing across queues or with the CPU, use the D3D12_BARRIER_ACCESS_GLOBAL access bit for proper cache coherency. See the specification for details.
Getting Started
Check for Fence Barriers support using CheckFeatureSupport with D3D12_FEATURE_FENCE_BARRIERS.
See the specification for complete feature detection code and detailed requirements.
Tier-2 Fence Barriers
While this preview focuses on Fence Barriers Tier-1, Tier-2 is actively in development. Tier-2 requires driver support for native fences and OS kernel support for user mode submission (in development).
What Tier-2 Will Bring
-
Full Cross-Queue
WaitBarrierSupport – Tier-1 restrictsWaitBarrierusage with fences that have bothD3D12_FENCE_FLAG_ALLOW_COMMAND_LIST_BARRIERSandD3D12_FENCE_FLAG_ALLOW_QUEUE_AND_CPU_SYNCflags set. Tier-2 removes this restriction, enabling seamlessWaitBarrieroperations across all queue types with any fence created withD3D12_FENCE_FLAG_ALLOW_COMMAND_LIST_BARRIERS. -
Enhanced CPU/GPU Synchronization – While Tier-1 focuses on Command List Scoped Fences, Tier-2 will provide full CPU/GPU synchronization capabilities through
WaitBarrier, making it easier to coordinate work between the CPU and GPU timelines. -
Advanced Hardware Features – Tier-2 requires kernel and driver support for user mode submission queues and native fences (sometimes referred to as “Hardware Scheduling Stage 3”), which enables more efficient fence operations at the hardware level.
Windows Version and Driver Support
Fence Barriers Tier-1 is supported on all Windows 11 release builds with the necessary driver updates.
Fence Barriers Tier-1 is supported in AMD Software: AgilitySDK Developer Preview Edition 25.30.21.01 and on Intel GPUs using the latest public drivers. Other GPU vendors are planning to support Tier-1 fence barriers soon.
We encourage you to experiment with Fence Barriers in your projects and share your feedback.
Thanks!
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