The PowerPC 600 series includes the following bitwise logical operations: <\/p>\n
\n and rd, ra, rb ; rd = ra & rb\n or rd, ra, rb ; rd = ra | rb\n xor rd, ra, rb ; rd = ra ^ rb\n nand rd, ra, rb ; rd = ~(ra & rb)\n nor rd, ra, rb ; rd = ~(ra | rb)\n eqv rd, ra, rb ; rd = ~(ra ^ rb)\n andc rd, ra, rb ; rd = ra & ~rb \"and complement\"\n orc rd, ra, rb ; rd = ra | ~rb \"or complement\"\n ; also \".\" versions\n<\/pre>\nEach of these instructions also comes with a dot variant that updates cr0<\/var> based on the result. <\/p>\n
There are also versions that take immediates or sometimes shifted immediates, and sometimes they update flags, and sometimes they don’t. There isn’t much orthogonality here. It’s all case-by-case. <\/p>\n
\n andi. rd, ra, imm16 ; rd = ra & (uint16_t)imm16, update cr0\n andis. rd, ra, imm16 ; rd = ra & ((uint16_t)imm16 << 16), update cr0\n ori rd, ra, imm16 ; rd = ra | (uint16_t)imm16\n oris rd, ra, imm16 ; rd = ra | ((uint16_t)imm16 << 16)\n xori rd, ra, imm16 ; rd = ra ^ (uint16_t)imm16\n xoris rd, ra, imm16 ; rd = ra ^ ((uint16_t)imm16 << 16)\n<\/pre>\nImmediates are allowed only on three of the bitwise operations, and the
and<\/code> version always updates flags, whereas theor<\/code> andxor<\/code> versions never update flags. <\/p>\nFor some reason, sign extension is placed in the logical operations group. <\/p>\n
\n extsb rd, ra ; rd = (int8_t)ra\n extsb. rd, ra ; rd = (int8_t)ra, update cr0\n extsh rd, ra ; rd = (int16_t)ra\n extsh. rd, ra ; rd = (int16_t)ra, update cr0\n<\/pre>\nWe now have enough instructions to load constants. <\/p>\n
If the constant is in the range
0xFFFF8000<\/code> to0x00007FFF<\/code>, it can be loaded in one instruction:<\/p>\n\n ; load immediate: rd = (int16_t)imm16\n addi rd, 0, imm16 ; li rd, imm16\n<\/pre>\nIt can also be done in one instruction if the constant is an exact multiple of 65536. <\/p>\n
\n ; load immediate shifted: rd = imm16 << 16\n addis rd, 0, imm16 ; lis rd, imm16\n<\/pre>\nThese take advantage of the fact that the
addi<\/code> andaddis<\/code> instructions treat r0<\/var> as if it were zero. They are the only non-memory instructions that have this special behavior with respect to r0<\/var>. <\/p>\nIf the constant you want to load doesn’t fall into either of the two categories above, then you’ll have to load it in two steps: <\/p>\n
\n addis rd, 0, imm16a ; rd = imm16a << 16\n ori rd, rd, imm16b ; rd = (imm16a << 16) | (uint16_t)imm16b\n<\/pre>\nThis sequence takes advantage of the fact that the
ori<\/code> instruction treats its 16-bit immediate as an unsigned value. That way, we don’t have to play funny games with the most significant 16 bits if the least-significant 16 bits happen to form a negative integer when interpreted as a signed 16-bit value. <\/p>\nWhile I’m here I may as well mention a third synthetic instruction based on
addi<\/code>: <\/p>\n\n ; load address: rd = effective address of imm16(ra)\n addi rd, ra, imm16 ; la rd, imm16(ra)\n<\/pre>\nA commonly-used synthetic instruction is “move register”: <\/p>\n
\n or rd, ra, ra ; mr rd, ra\n or. rd, ra, ra ; mr. rd, ra\n<\/pre>\nMoving a register to itself is functionally a nop, but the processor overloads it to signal information about priority. <\/p>\n
\n or r1, r1, r1 ; low priority\n or r6, r6, r6 ; medium-low priority\n or r2, r2, r2 ; normal priority\n<\/pre>\nA program can voluntarily set itself to low priority if it is waiting for a spin lock. There are other priority levels which are available only to kernel mode and are ignored in user mode. <\/p>\n
Finally, everybody’s favorite instruction: <\/p>\n
\n ori r0, r0, 0 ; nop\n<\/pre>\nThis is the official
nop<\/code> instruction recognized by the processor. There are other instructions that have no visible effect, but they might not be optimized efficiently. For example,rlwinm ra, ra, 0, 0, 31<\/code> has no visible effect, but it will probably introduce a register dependency. And as we saw above, sometimes instructions with no visible effect become overloaded as signals to the processor, so your best bet is to avoid them. <\/p>\n