Continuing in the “Raymond introduces you to a CPU architecture that Windows once supported but no longer does” sort-of series, here we go with the MIPS R4000. <\/p>\n
The MIPS R4000 implements the MIPS III architecture. It is a 64-bit processor, but Windows NT used it in 32-bit mode. I’ll be focusing on the aspects of the processor relevant to debugging user-mode programs on Windows NT. This means that I may skip over various technical details on the assumption that the compiler knows what the rules are and won’t (intentionally) generate code that violates them. <\/p>\n
Throughout, I will say “MIPS” instead of “MIPS III architecture”. Some of the issues do not apply to later versions of the architecture family, but I am focusing on MIPS III since that’s what Windows NT used. <\/p>\n
The MIPS is a RISC-style load-store processor: The only operations you can perform with memory are load and store. There is no “add value to memory” instruction, for example. Each instruction is 32 bits wide, and the program counter must be on an exact multiple of 4. <\/p>\n
The processor can operate in either little-endian or big-endian mode; Windows NT uses little-endian mode, and even though some instructions change behavior depending on whether the processor is in big-endian or little-endian mode, I will discuss only the little-endian case. <\/p>\n
The architectural terminology for a 32-bit value is a word<\/i> (w), and a 16-bit value is a halfword<\/i> (h). There’s also doubleword<\/i> (d) for 64-bit values, but we won’t see it here because we are focusing on the 32-bit mode of the processor. <\/p>\n
The MIPS has 32 general-purpose integer registers, formally known as registers $0<\/var> through $31<\/var>, but which conventionally go by these names: <\/p>\n