cc<\/u><\/code> represents one of the above condition codes. <\/p>\nThe conditional move instructions test a source register against a condition, and if the condition is true, the destination register receives the second source. <\/p>\n
\n CMOVcc<\/u> Ra, Rb\/#b, Rc ; if Ra meets condition, then Rc = Rb\/#b\n<\/pre>\nYou can also generate booleans from conditions. Note that the set of conditions here is not the same as the standard set of conditions above! <\/p>\n
\n CMPEQ Ra, Rb\/#b, Rc ; Rc = (Ra == Rb\/#b)\n CMPLT Ra, Rb\/#b, Rc ; Rc = (Ra < Rb\/#b) signed comparison\n CMPLE Ra, Rb\/#b, Rc ; Rc = (Ra ≤ Rb\/#b) signed comparison\n CMPULT Ra, Rb\/#b, Rc ; Rc = (Ra < Rb\/#b) unsigned comparison\n CMPULE Ra, Rb\/#b, Rc ; Rc = (Ra ≤ Rb\/#b) unsigned comparison\n<\/pre>\nThese comparison operators produce values of exactly 0 or 1, according to the result of the comparison, and the comparison is against the full 64-bit register value. <\/p>\n
Conditional jump instructions provide a condition and a register, as well as a jump target. <\/p>\n
\n Bcc<\/u> Ra, destination\n<\/pre>\nwhere cc<\/u><\/code> is one of the condition codes above. The instruction tests the specified register against the condition, and if true, control is transferred to the destination. The test is against the full 64-bit register value, and the destination is encoded as a 21-bit value, in units of instructions (4 bytes), which provides a reach of ±4MB. <\/p>\nConditional branches backward are predicted taken. Conditional branches forward are predicted not taken. <\/p>\n
There are two types of unconditional branches. They are functionally the same but have different consequences for the return address predictor. <\/p>\n
\n BR Ra, destination ; not expected to return\n BSR Ra, destination ; expected to return\n<\/pre>\nThese instructions store the address of the subsequent instruction (the return address) in the Ra<\/var> register and then transfer to the destination. The BR<\/code> instruction does not push the return address onto the return address predictor stack; the BSR<\/code> instruction does. <\/p>\nThe BR<\/code> instruction is typically used with zero<\/var> as the register to receive the return address, since the value is almost always thrown away. (Recall that there is a special exemption for branch instructions to the usual rule that instructions which write to zero<\/var> can be optimized away.) <\/p>\nThe Win32 calling convention dictates that the ra<\/var> register holds the return address on entry to a function. <\/p>\nThere are four indirect jump instructions which are all functionally equivalent but differ in their effect on the return address predictor. <\/p>\n
\n JMP Ra, (Rb), hint16 ; not expected to return\n JSR Ra, (Rb), hint16 ; expected to return\n RET Ra, (Rb), hint16 ; end of function\n JSR_CO Ra, (Rb), hint16 ; coroutine\n<\/pre>\nThe Ra<\/var> register receives the return address, typically zero<\/var> in the case of JMP<\/code> and RET<\/code>, and conventionally ra<\/var> in the case of JSR<\/code>. As you have probably guessed, JMP<\/code> has no effect on the return address predictor, JSR<\/code> pushes the return address onto the predictor stack, and RET<\/code> pops the return address off of the predictor stack and predicts a transfer to the popped value. The weird guy is JSR_CO<\/code> which replaces the return address at the top of the predictor stack with the new return address and predicts a transfer to the old value. <\/p>\nThe official name of JSR_CO<\/code> is JSR_<\/code>COROUTINE<\/code>, but it doesn’t really matter because I have never see JSR_CO<\/code> in practice. <\/p>\nFor the JMP<\/code> and JSR<\/code> instructions, the “hint” is a static prediction of the low 16 bits of the value in Rb<\/var>. <\/p>\nThe RET<\/code> and JSR_CO<\/code> instructions don’t need a hint because they have their own return address predictor. However, DEC recommends that the hint for a RET<\/code> instruction be 1 for a return from a procedure, and 0 otherwise. We’ll see more about this another day. <\/p>\nThe Microsoft compiler doesn’t generate hints; it just sets the hint to zero. Profile-guided optimization didn’t come to Visual C++ until after support for the Alpha AXP was dropped, but if it were still in support, I’m assuming that profile-guided optimization would have filled in the hint. <\/p>\n
Non-virtual calls will look generally like this: <\/p>\n
\n ; Put the parameters in a0 through a5\n ; by whatever means appropriate.\n ; Excess parameters go on the stack.\n ; (Not shown here.)\n BIS zero, s1, a0 ; copied from another register\n LDL a1, 32(sp) ; loaded from memory\n ADDL zero, #1, a2 ; calculated in place\n\n BSR ra, destination ; call the other function\n ; result is in the v0 register\n<\/pre>\nVirtual calls load the destination from the target’s vtable: <\/p>\n
\n ; Put the parameters in a0 through a5\n ; by whatever means appropriate.\n ; Excess parameters go on the stack.\n ; (Not shown here.)\n ; \"this\" goes into a0.\n BIS zero, s1, a0 ; copied from another register\n LDL a1, 32(sp) ; loaded from memory\n ADDL zero, #1, a2 ; calculated in place\n\n LDL t0, (a0) ; load vtable\n LDL t0, 8(t0) ; load function from vtable\n BSR ra, (t0) ; call the function pointer\n ; result is in the v0 register\n<\/pre>\nCalls to exported functions are indirect through a global variable, which means we need to get the address of that global. <\/p>\n
\n ; Put the parameters in a0 through a5\n ; by whatever means appropriate.\n ; Excess parameters go on the stack.\n ; (Not shown here.)\n BIS zero, s1, a0 ; copied from another register\n LDL a1, 32(sp) ; loaded from memory\n ADDL zero, #1, a2 ; calculated in place\n\n LDAH t0, xxxx(zero) ; 64KB block where global variable resides\n LDL t0, yyyy(t0) ; load the global variable\n BSR ra, (t0) ; call the function pointer\n ; result is in the v0 register\n<\/pre>\nThe above examples use the LDL<\/code> instruction, which loads a register from memory. We’ll learn more about memory access next time. <\/p>\n","protected":false},"excerpt":{"rendered":"But there is no flags register.<\/p>\n","protected":false},"author":1069,"featured_media":111744,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[26],"class_list":["post-96805","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-oldnewthing","tag-other"],"acf":[],"blog_post_summary":"
But there is no flags register.<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/96805","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/users\/1069"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/comments?post=96805"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/96805\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media\/111744"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media?parent=96805"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/categories?post=96805"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/tags?post=96805"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}