{"id":107954,"date":"2023-03-21T07:00:00","date_gmt":"2023-03-21T14:00:00","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/oldnewthing\/?p=107954"},"modified":"2023-03-21T08:41:13","modified_gmt":"2023-03-21T15:41:13","slug":"20230321-00","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/oldnewthing\/20230321-00\/?p=107954","title":{"rendered":"Why does the usage of the initial registers of a Win32 process depend on whether it is a 32-bit or 64-bit process?"},"content":{"rendered":"

Someone noticed that when you create a process suspended and snoop at its registers, the results vary depending on wither it is a 32-bit or 64-bit process.<\/p>\n

For a 32-bit process, the initial register state puts something in eax<\/code> and something else in ebx<\/code>.<\/p>\n

For a 64-bit process, the initial register state puts something in rcx<\/code> and something else in rdx<\/code>.<\/p>\n

Why do 32-bit and 64-bit processes use different registers to pass the initial state? Either make the 32-bit initial state use ecx<\/code> and edx<\/code>, or make the 64-bit initial state use rax<\/code> and rbx<\/code>. This appears to be an intentional divergence. What’s the reason for it?<\/p>\n

First of all, note that all of what I’m writing here is internal implementation detail that can change at any time. I’m discussing it to satisfy your curiosity, not to provide information that you can rely on.<\/p>\n

Okay, so back to the question. Why do 32-bit and 64-bit processes disagree?<\/p>\n

Well, really, the question is “What makes you think they should agree?”<\/p>\n

I sort of hid an assumption in the question. Did you spot it?<\/p>\n

The customer is asking not about 32-bit and 64-bit Windows, but about the x86-32 and x86-64 processor architectures. The question is based on a limited understanding of the world of CPUs. “We got both kinds. We got x86-32 and<\/i> x86-64<\/a>!”<\/p>\n

Windows has supported many 32-bit processor architectures, and I’ve covered many of them in the past: x86-32<\/a>, Alpha AXP<\/a>, MIPS III<\/a>, PowerPC<\/a>, SuperH-3<\/a>, and ARM<\/a>. It also has supported a number of 64-bit processor architectures, including Alpha AXP<\/a> (using all 64 bits this time), Itanium<\/a>, x86-64<\/a>, and AArch64<\/a>.<\/p>\n

All of these architectures are different, and there’s no a priori<\/i> expectation that any two of them match up in register usage in any particular way.<\/p>\n

Here’s a comparison of calling conventions, with a lot of details omitted.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
32-bit architectures<\/th>\nx86-32<\/th>\nAlpha AXP<\/th>\nMIPS III<\/th>\nPowerPC<\/th>\nSuperH-3<\/th>\nARM<\/th>\n<\/tr>\n
iarg1<\/td>\n[esp<\/var>+4]<\/td>\na0<\/var><\/td>\na0<\/var><\/td>\nr3<\/var><\/td>\nr4<\/var><\/td>\na1<\/var><\/td>\n<\/tr>\n
iarg2<\/td>\n[esp<\/var>+8]<\/td>\na1<\/var><\/td>\na1<\/var><\/td>\nr4<\/var><\/td>\nr5<\/var><\/td>\na2<\/var><\/td>\n<\/tr>\n
iarg3<\/td>\n[esp<\/var>+12]<\/td>\na2<\/var><\/td>\na2<\/var><\/td>\nr5<\/var><\/td>\nr6<\/var><\/td>\na3<\/var><\/td>\n<\/tr>\n
iarg4<\/td>\n[esp<\/var>+16]<\/td>\na3<\/var><\/td>\na3<\/var><\/td>\nr6<\/var><\/td>\nr7<\/var><\/td>\na4<\/var><\/td>\n<\/tr>\n
iarg5<\/td>\n[esp<\/var>+20]<\/td>\na4<\/var><\/td>\na4<\/var><\/td>\nr7<\/var><\/td>\n@(16, r15<\/var>)<\/td>\n[sp<\/var>, #0]<\/td>\n<\/tr>\n
iarg6<\/td>\n[esp<\/var>+24]<\/td>\na5<\/var><\/td>\n20(sp<\/var>)<\/td>\nr8<\/var><\/td>\n@(20, r15<\/var>)<\/td>\n[sp<\/var>, #4]<\/td>\n<\/tr>\n
iarg7<\/td>\n[esp<\/var>+28]<\/td>\n0(sp<\/var>)<\/td>\n24(sp<\/var>)<\/td>\nr9<\/var><\/td>\n@(24, r15<\/var>)<\/td>\n[sp<\/var>, #8]<\/td>\n<\/tr>\n
iarg8<\/td>\n[esp<\/var>+32]<\/td>\n8(sp<\/var>)<\/td>\n28(sp<\/var>)<\/td>\nr10<\/var><\/td>\n@(28, r15<\/var>)<\/td>\n[sp<\/var>, #12]<\/td>\n<\/tr>\n
iarg9<\/td>\n[esp<\/var>+36]<\/td>\n16(sp<\/var>)<\/td>\n32(sp<\/var>)<\/td>\n32(r1<\/var>)<\/td>\n@(32, r15<\/var>)<\/td>\n[sp<\/var>, #16]<\/td>\n<\/tr>\n
fpargs<\/td>\non stack<\/td>\nf16<\/var>\u2026f21<\/var><\/td>\nf12<\/var>\u2026f15<\/var><\/td>\nf1<\/var>\u2026f13<\/var><\/td>\nfr4<\/var>\u2026fr7<\/var><\/td>\nd0<\/var>\u2026d7<\/var><\/td>\n<\/tr>\n
iret<\/td>\neax<\/var>, edx<\/var><\/td>\nv0<\/var><\/td>\nv0<\/var>, v1<\/var><\/td>\nr3<\/var><\/td>\nr0<\/var><\/td>\na1<\/var>, a2<\/var><\/td>\n<\/tr>\n
fpret<\/td>\nst(0)<\/var>, st(1)<\/var><\/td>\nf0<\/var>, f1<\/var><\/td>\nf0<\/var>\/f1<\/var>, f2<\/var>\/f3<\/var><\/td>\nf1<\/var><\/td>\nfr0<\/var><\/td>\nd0<\/var>, d1<\/var><\/td>\n<\/tr>\n
home space?<\/td>\nno<\/td>\nno<\/td>\nyes<\/td>\nyes<\/td>\nyes<\/td>\nno<\/td>\n<\/tr>\n
i\/fp separate alloc<\/td>\nno<\/td>\nyes<\/td>\nno<\/td>\nyes<\/td>\nsort-of<\/td>\nyes<\/td>\n<\/tr>\n
reuse partial fp regs<\/td>\nno<\/td>\nno<\/td>\nno<\/td>\nno<\/td>\nyes<\/td>\nyes<\/td>\n<\/tr>\n
stack alignment<\/td>\n4<\/td>\n16<\/td>\n8<\/td>\n8<\/td>\n4<\/td>\n8<\/td>\n<\/tr>\n
red zone<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n232<\/td>\n0<\/td>\n8<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

And for 64-bit architectures:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
64-bit architectures<\/th>\nAlpha AXP<\/th>\nItanium<\/th>\nx86-64<\/th>\nAArch64<\/th>\n<\/tr>\n
iarg1<\/td>\na0<\/var><\/td>\nr32<\/var><\/td>\nrcx<\/var><\/td>\nx0<\/var><\/td>\n<\/tr>\n
iarg2<\/td>\na1<\/var><\/td>\nr33<\/var><\/td>\nrdx<\/var><\/td>\nx1<\/var><\/td>\n<\/tr>\n
iarg3<\/td>\na2<\/var><\/td>\nr34<\/var><\/td>\nr8<\/var><\/td>\nx2<\/var><\/td>\n<\/tr>\n
iarg4<\/td>\na4<\/var><\/td>\nr35<\/var><\/td>\nr9<\/var><\/td>\nx3<\/var><\/td>\n<\/tr>\n
iarg5<\/td>\na4<\/var><\/td>\nr36<\/var><\/td>\n[rsp<\/var>+32]<\/td>\nx4<\/var><\/td>\n<\/tr>\n
iarg6<\/td>\na5<\/var><\/td>\nr37<\/var><\/td>\n[rsp<\/var>+40]<\/td>\nx5<\/var><\/td>\n<\/tr>\n
iarg7<\/td>\n0(sp<\/var>)<\/td>\nr38<\/var><\/td>\n[rsp<\/var>+48]<\/td>\nx6<\/var><\/td>\n<\/tr>\n
iarg8<\/td>\n8(sp<\/var>)<\/td>\nr39<\/var><\/td>\n[rsp<\/var>+56]<\/td>\nx7<\/var><\/td>\n<\/tr>\n
iarg9<\/td>\n16(sp<\/var>)<\/td>\n[sp<\/var>]<\/td>\n[rsp<\/var>+64]<\/td>\n[sp<\/var>, #0]<\/td>\n<\/tr>\n
fpargs<\/td>\nf16<\/var>\u2026f21<\/var><\/td>\nf32<\/var>\u2026f39<\/var><\/td>\nxmm0<\/var>\u2026xmm3<\/var><\/td>\nv0<\/var>\u2026v7<\/var><\/td>\n<\/tr>\n
iret<\/td>\nv0<\/var><\/td>\nret0<\/var>\u2026ret3<\/var><\/td>\nrax<\/var><\/td>\nx0<\/var><\/td>\n<\/tr>\n
fpret<\/td>\nf0<\/var>, f1<\/var><\/td>\nf8<\/var><\/td>\nxmm0<\/var><\/td>\nd0<\/var>, d1<\/var><\/td>\n<\/tr>\n
home space?<\/td>\nno<\/td>\nno<\/td>\nyes<\/td>\nno<\/td>\n<\/tr>\n
i\/fp separate alloc<\/td>\nyes<\/td>\nyes<\/td>\nno<\/td>\nyes<\/td>\n<\/tr>\n
reuse partial fp regs<\/td>\nno<\/td>\nno<\/td>\nno<\/td>\nno<\/td>\n<\/tr>\n
stack alignment<\/td>\n16<\/td>\n16<\/td>\n16<\/td>\n16<\/td>\n<\/tr>\n
red zone<\/td>\n0<\/td>\n\u221216<\/a><\/td>\n0<\/td>\n16<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Certainly you don’t expect all of these process to agree on what registers to use. They don’t even all have the same registers to begin with!<\/p>\n

Okay, so maybe the question is “Yes, I know that Windows supports more than just x86-32 and x86-64, but the two architectures are clearly descended from each other, so why are things so different between them?”<\/p>\n

Well, why should they be the same? After all, x86-32 descended from 8086, but it’s not like we still using the 8086 calling convention in x86-64 code. With a newer processor, we can take advantage of newer features, and that means we can re-optimize the calling convention to take advantage of them<\/a>: Use the SSE registers for floating point instead of the legacy st(n)<\/var> registers. Use compile-time exception handling tables instead of run-time stack threading. Increase the stack alignment requirements to be SSE-friendly. Pass parameters in registers rather than on the stack, now that we are no longer under severe register pressure.<\/p>\n

We also see changes when moving from 32-bit ARM to 64-bit AArch64: The number of register-based parameters increases from four to eight, the partial floating point register backfill was dropped, the stack alignment became stricter, and the red zone expanded.<\/p>\n

I mean, clearly you have to change something<\/i> because the 64-bit registers are bigger than the 32-bit registers. At a minimum, you’ll have to expand the register sizes. And once you decide to expand the register sizes, you’ve committed to the cost of change, so you may as well get your money’s worth.<\/p>\n

One thing you might notice is that the 32-bit and 64-bit Alpha AXP calling conventions are identical. What happened here? Was the 32-bit calling convention so perfect that nothing had to be improved for the 64-bit convention? What about the whole “expanding registers from 32-bit to 64-bit requires a change at least for the new register sizes”?<\/p>\n

Recall that the Alpha AXP was always a 64-bit processor. There was no 32-bit Alpha AXP processor. The “32-bit” Alpha AXP calling convention was developed with a 64-bit processor in hand, just with the understanding that pointers are only 32 bits in size, for now. (Though you could ask for memory in the parts of the address space that require the use of 64-bit pointers<\/a>. It would then be on you to figure out how to cajole the compiler into using 64-bit pointers<\/a>.)<\/p>\n

When the 32-bit ABI for Alpha AXP was invented, the processor already had 64-bit registers and full support for 64-bit operations. It’s just that 32-bit Windows voluntarily restricted itself to 32 bits of address space. When designing the calling convention, the ABI designers made parameters 64-bit values, even if only the lower 32 bits were significant in practice. Everything was carefully designed so that the 32-bit calling convention could be repurposed as a 64-bit calling convention without any changes.\u00b9 (This came in handy when the Alpha AXP was used as a proof-of-concept hardware platform for 64-bit Windows<\/a>, since it avoided having to change large portions of the compiler.) In other words, the 32-bit ABI for Alpha AXP was invented with the power of clairvoyance: They knew what the 64-bit process was going to look like, and they could design the 32-bit ABI to be identical to the 64-bit one.<\/p>\n

One thing you may notice is that all of the calling conventions pass parameters in registers except for one: x86-32. Once again, the x86 is the weirdo<\/a>. The internal kernel infrastructure for creating a process lets you specify an initial register state and an initial instruction pointer, but it doesn’t let you describe the contents of the stack. This means that all parameters must be passed in registers. This is straightforward for the register-based calling conventions, since they can just put the parameters directly in the initial register state. But for x86-32, that doesn’t work.<\/p>\n

What happens on x86-32 is that the kernel puts the parameters in some dummy registers, and then sets the initial instruction pointer not to the start of the process but rather to a helper function written in assembly language that takes those values from registers, pushes them onto the stack (to conform with the x86-32 calling convention), and then calls the real<\/i> process start function.<\/p>\n

The registers to use for this “custom calling convention” are completely arbitrary, and the kernel folks chose eax<\/var> and ebx<\/var> out of alphabetical convenience.\u00b2 This choice was made several decades before the x86-64 convention was invented, so there was nothing to be compatible with.<\/p>\n

So that’s the reason why the x86-32 and x86-64 architectures disagree on how to pass the initial parameters to the process. There was no reason why they had to agree in the first place. The 32-bit version picked two registers arbitrarily, and those didn’t happen to correspond in an attractive way with the x86-64 calling convention that would come later.\u00b3<\/p>\n

\u00b9 In theory, this would even let 32-bit and 64-bit Alpha AXP code coexist within a process, since they could just call into each other without having to do any calling convention thunking. The 64-bit code would have to be careful to pass only pointers to memory addressible with 32-bit pointers.<\/p>\n

\u00b2 What the kernel folks could have done was declare the process start function as using the __fastcall<\/code> calling convention<\/a>, which takes the first two parameters in ecx<\/code> and edx<\/code>. That would have avoided having to write the little helper function.<\/p>\n

\u00b3 I guess you could turn the question around and ask “Why doesn’t the x86-64 calling convention use rax<\/code> and rbx<\/code> for the first two register parameters, so it would align in an attractive manner with the custom calling convention used by this one specific corner of the kernel.” That was a one-off dark corner of the kernel that uses a custom calling convention that only a handful of people even know about, so there’s no reason that the people who designed the x86-64 calling convention even knew about it, much less possessed any desire to align with it in an attractive manner. And even if they knew about it, there’s really no need to accommodate it when designing a calling convention for general-purpose computing. There are probably quite a few one-off custom calling conventions scattered around the system. The one used by the kernel for starting new processes isn’t particularly prominent. (Indeed, it’s so deeply buried that it’s probably one of the most obscure<\/i> ones.)<\/p>\n","protected":false},"excerpt":{"rendered":"

Well, I mean, it’s a different processor.<\/p>\n","protected":false},"author":1069,"featured_media":111744,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[26],"class_list":["post-107954","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-oldnewthing","tag-other"],"acf":[],"blog_post_summary":"

Well, I mean, it’s a different processor.<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/107954","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/users\/1069"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/comments?post=107954"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/107954\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media\/111744"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media?parent=107954"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/categories?post=107954"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/tags?post=107954"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}