{"id":106968,"date":"2022-08-12T07:00:00","date_gmt":"2022-08-12T14:00:00","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/oldnewthing\/?p=106968"},"modified":"2022-09-16T06:08:42","modified_gmt":"2022-09-16T13:08:42","slug":"20220812-00","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/oldnewthing\/20220812-00\/?p=106968","title":{"rendered":"The AArch64 processor (aka arm64), part 14: Barriers"},"content":{"rendered":"

Barriers are important on ARM-family systems because it has a weak memory model<\/a> compared to the x86 series that most people are familiar with.<\/p>\n

We start with the explicit barrier instructions:<\/p>\n

    dmb     ish     ; data memory barrier\r\n    dsb     ish     ; data synchronization barrier\r\n    isb     sy      ; instruction synchronization barrier\r\n<\/pre>\n
The data memory barrier ensures that all preceding writes are issued before any subsequent memory operations (including speculative memory access). In acquire\/release terms, it is a full barrier. The instruction does not stall execution; it just tells the memory controller to preserve externally-visible ordering. This is probably the only barrier you will ever seen in user-mode code.<\/p>\n
The data synchronization barrier is a data memory barrier, but with the additional behavior of stalling until all outstanding writes have completed. This is typically used before changing memory mappings, such as during context switches, to ensure that any outstanding writes complete to the original memory before it gets unmapped.<\/p>\n
The instruction synchronization barrier flushes instruction prefetch. This is typically used if you have generated new code, say by jitting it or paging it in from disk.<\/p>\n
All of these barrier instructions take a parameter known as the synchronization domain<\/i>. In practice, they will be the values I gave in the examples above.<\/p>\n
There are some other niche barriers like the “consumption of speculative data barrier” (CSDB<\/code>) and “physical speculative store bypass barrier” (PSSBB<\/code>), which I won’t bother going into because you’re not going to see them.<\/p>\n
By default, the memory access instructions do not impose any special ordering. But there are variations that let you request acquire or release semantics. We saw the general pattern in the bonus chatter last time:<\/p>\n