Since AArch64 uses fixed-size 32-bit instructions, you have to exercise some creativity to load a 64-bit constant.<\/p>\n
; move wide with zero\r\n ; Rd = imm16 << n\r\n ; n can be 0, 16, 32, or 48\r\n movz Rd, #imm16, LSL #n\r\n\r\n ; move wide with not\r\n ; Rd = ~(imm16 << n)\r\n ; n can be 0, 16, 32, or 48\r\n movn Rd, #imm16, LSL #n\r\n\r\n ; move wide with keep\r\n ; Rd[n+15:n] = imm16\r\n movk Rd, #imm16, LSL #n\r\n<\/pre>\nThe
MOVZ<\/code> instruction loads a 16-bit unsigned value into one of the four lanes of a 64-bit destination, or one of the two lanes of a 32-bit destination. All the remaining lanes are set to zero.<\/p>\nThe
MOVN<\/code> instruction does the same thing asMOVZ<\/code>, except the whole thing is bitwise negated. (Be careful not to confuseMOVN<\/code> withMVN<\/code>.)<\/p>\nThe
MOVK<\/code> instruction does the same thing asMOVZ<\/code>, except that instead of setting the other lanes to zero, the other lanes are left unchanged.<\/p>\nLoading a 32-bit value can be done in two instructions by using
MOVZ<\/code> to load 16 bits into half of the register, than theMOVK<\/code> into the other half.<\/p>\nmovz r0, #0x1234 ; r0 = 0x00001234\r\n movk r0, #0xABCD, LSL #16 ; r0 = 0xABCD1234\r\n<\/pre>\nThis technique can be extended to load a 64-bit value in four steps, but that’s getting quite unwieldy. The compiler is more likely to store the value in the code segment and use a pc<\/var>-relative addressing mode to load it.<\/p>\n
; special syntax for pc-relative loads\r\n ldr x0, =0x123456789ABCDEF0 ; load 64-bit value\r\n ldr w0, =0x12345678 ; load 32-bit value\r\n<\/pre>\nAs I noted in the discussion of addressing modes, the assembler and disassembler use this special equals-sign notation to represent a pc<\/var>-relative load. It means that the value is stored in a literal pool<\/var> in the code segment, and a pc<\/var>-relative load is being used to fetch it. The assembler batches up all of these literals and emits them between functions. The pc<\/var>-relative load has a reach of \u00b11MB, so you are unlikely to run into the problem that you had on AArch32, where the reach was only \u00b14KB, and you had to find a safe place to dump the literals in the middle of the function.<\/p>\n
There are quite a number of instructions that generate constants, and if you use the
MOV<\/code> pseudo-instruction, the assembler will try to find one that works.<\/p>\n; load up a constant somehow\r\n mov Rd, #imm\r\n<\/pre>\n\n\n
\n Instruction<\/th>\n Used for<\/th>\n<\/tr>\n \n add Rd, zr, #imm12<\/code><\/td>\n0x00000000`00000XXX<\/code><\/td>\n<\/tr>\n\n add Rd, zr, #imm12, LSL #12<\/code><\/td>\n0x00000000`00XXX000<\/code><\/td>\n<\/tr>\n\n sub Wd, wzr, #imm12<\/code><\/td>\n0x00000000`FFFFFXXX<\/code><\/td>\n<\/tr>\n\n sub Wd, wzr, #imm12, LSL #12<\/code><\/td>\n0x00000000`FFXXXFFF<\/code><\/td>\n<\/tr>\n\n sub Xd, xzr, #imm12<\/code><\/td>\n0xFFFFFFFF`FFFFFXXX<\/code><\/td>\n<\/tr>\n\n sub Xd, xzr, #imm12, LSL #12<\/code><\/td>\n0xFFFFFFFF`FFXXXFFF<\/code><\/td>\n<\/tr>\n\n movz Rd, #imm16<\/code><\/td>\n0x00000000`0000XXXX<\/code><\/td>\n<\/tr>\n\n movz Rd, #imm16, LSL #16<\/code><\/td>\n0x00000000`XXXX0000<\/code><\/td>\n<\/tr>\n\n movz Rd, #imm16, LSL #32<\/code><\/td>\n0x0000XXXX`00000000<\/code><\/td>\n<\/tr>\n\n movz Rd, #imm16, LSL #48<\/code><\/td>\n0xXXXX0000`00000000<\/code><\/td>\n<\/tr>\n\n movn Wd, #imm16<\/code><\/td>\n0x00000000`FFFFXXXX<\/code><\/td>\n<\/tr>\n\n movn Wd, #imm16, LSL #16<\/code><\/td>\n0x00000000`XXXXFFFF<\/code><\/td>\n<\/tr>\n\n movn Xd, #imm16<\/code><\/td>\n0xFFFFFFFF`FFFFXXXX<\/code><\/td>\n<\/tr>\n\n movn Xd, #imm16, LSL #16<\/code><\/td>\n0xFFFFFFFF`XXXXFFFF<\/code><\/td>\n<\/tr>\n\n movn Xd, #imm16, LSL #32<\/code><\/td>\n0xFFFFXXXX`FFFFFFFF<\/code><\/td>\n<\/tr>\n\n movn Xd, #imm16, LSL #48<\/code><\/td>\n0xXXXXFFFF`FFFFFFFF<\/code><\/td>\n<\/tr>\n\n orr Xd, xzr, #imm<\/code><\/td>\nValue can be expressed as a Bitwise operation constant<\/td>\n<\/tr>\n \n orr Wd, wzr, #imm<\/code><\/td>\nValue can be expressed as lower 32 bits of a Bitwise operation constant<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n A common type of sort-of constant is the address of a global variable. It’s a constant whose value isn’t discovered until runtime. We’ll look at those next time.<\/p>\n","protected":false},"excerpt":{"rendered":"
Getting them into a register.<\/p>\n","protected":false},"author":1069,"featured_media":111744,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[2],"class_list":["post-106953","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-oldnewthing","tag-history"],"acf":[],"blog_post_summary":"
Getting them into a register.<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/106953","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/users\/1069"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/comments?post=106953"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/106953\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media\/111744"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media?parent=106953"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/categories?post=106953"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/tags?post=106953"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}