{"id":106927,"date":"2022-08-02T07:00:00","date_gmt":"2022-08-02T14:00:00","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/oldnewthing\/?p=106927"},"modified":"2022-08-02T06:38:22","modified_gmt":"2022-08-02T13:38:22","slug":"20220802-00","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/oldnewthing\/20220802-00\/?p=106927","title":{"rendered":"The AArch64 processor (aka arm64), part 6: Bitwise operations"},"content":{"rendered":"

Bitwise logical operations are not normally particularly exciting, but for AArch64, they get exciting not so much for the operations themselves but for the immediates they can encode.<\/p>\n

Let’s get the boring part out of the way.<\/p>\n

    ; bitwise and with immediate\r\n    ; Rd = Rn & imm\r\n    and     Rd\/sp, Rn\/zr, #imm\r\n\r\n    ; bitwise and with shifted register\r\n    ; Rd = Rn & (Rm with shift)\r\n    and     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise and with immediate, set flags\r\n    ; Rd = Rn & #imm, set flags\r\n    ands    Rd\/zr, Rn\/zr, #imm\r\n\r\n    ; bitwise and with shifted register, set flags\r\n    ; Rd = Rn & (Rm with shift), set flags\r\n    ands    Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise clear\r\n    ; Rd = Rn & ~(Rm with shift)\r\n    bic     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise clear, set flags\r\n    ; Rd = Rn & ~(Rm with shift), set flags\r\n    bics    Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise or with immediate\r\n    ; Rd = Rn | imm\r\n    orr     Rd\/sp, Rn\/zr, #imm\r\n\r\n    ; bitwise or with shifted register\r\n    ; Rd = Rn | (Rm with shift)\r\n    orr     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise or not with shifted register\r\n    ; Rd = Rn | ~(Rm with shift)\r\n    orn     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise exclusive or with immediate\r\n    ; Rd = Rn ^ imm\r\n    eor     Rd\/sp, Rn\/zr, #imm\r\n\r\n    ; bitwise exclusive or with shifted register\r\n    ; Rd = Rn ^ (Rm with shift)\r\n    eor     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    ; bitwise exclusive or not with shifted register\u00b9\r\n    ; Rd = Rn ^ ~(Rm with shift)\r\n    eon     Rd\/zr, Rn\/zr, Rm\/zr, shift\r\n<\/pre>\n
There are a lot of combinations here. Let’s put them in a table.<\/p>\n\n\n\n\n\n\n\n\n\n\n
Instruction<\/th>\nImmediate<\/th>\nShifted register<\/th>\n<\/tr>\n
to Rd\/sp
\nno flags<\/th>\n		to Rd\/zr
\nwith flags<\/th>\n		to Rd\/zr
\nno flags<\/th>\n		to Rd\/zr
\nwith flags<\/th>\n<\/tr>\n
AND<\/code><\/td>\n\u2022<\/td>\n\u2022<\/td>\n\u2022<\/td>\n\u2022<\/td>\n<\/tr>\n
BIC<\/code><\/td>\n <\/td>\n <\/td>\n\u2022<\/td>\n\u2022<\/td>\n<\/tr>\n
ORR<\/code><\/td>\n\u2022<\/td>\n <\/td>\n\u2022<\/td>\n <\/td>\n<\/tr>\n
ORN<\/code><\/td>\n <\/td>\n <\/td>\n\u2022<\/td>\n <\/td>\n<\/tr>\n
EOR<\/code><\/td>\n\u2022<\/td>\n <\/td>\n\u2022<\/td>\n <\/td>\n<\/tr>\n
EON<\/code><\/td>\n <\/td>\n <\/td>\n\u2022<\/td>\n <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
For the instructions that set flags, the N and Z flags represent the result of the operation, and the C and V flags are cleared.\u00b2<\/p>\n
Stare at this table a bit and you start to see patterns.<\/p>\n
All of the bitwise operations support a shifted register, which could be a LSL #0<\/code> to mean “no shift”. The operations that do not complement the second input operand support an immediate. (There’s no need to support an immediate for the complement versions, because you can just complement the immediate.) And the AND<\/code>-like operations are the only ones which support flags. We’ll see workarounds for the lack of flags support in the other bitwise operations when we get to control transfer.<\/p>\n
With these instructions, we can create some pseudo-instructions:\u00b3<\/p>\n
    tst     Rn\/zr, #imm             ; ands zr, Rn\/zr, #imm\r\n    tst     Rn\/zr, Rm\/zr, shift     ; ands zr, Rn\/zr, Rm\/zr, shift\r\n\r\n    mov     Rd, #imm                ; orr  Rd, zr, #imm\r\n    mov     Rd, Rn\/zr, shift        ; orr  Rd, zr, Rn\/zr, shift\r\n\r\n    mvn     Rd, Rn\/zr, shift        ; orn  Rd, zr, Rn\/zr, shift\r\n<\/pre>\n
The TST<\/code> pseudo-instruction performs a bitwise and<\/i> of its arguments and sets flags, but discards the result. It’s common to use a power-of-two immediate here, to test a specific bit.<\/p>\n
The MOV<\/code> instruction set a register equal to the value of another register or a supported immediate.<\/p>\n
The MVN<\/code> instruction sets a register to the bitwise inverse of another register.<\/p>\n
Okay, so about those immediates.<\/p>\n
The bitwise operations encode the immediates in a very strange way. If that’s the sort of thing that interests you, I encourage you to read  Dominik Inf\u00fchr’s explanation of how they are formed<\/a> for the gory details.<\/p>\n
The short version is that the immediate can encode<\/p>\n