{"id":106912,"date":"2022-07-28T07:00:00","date_gmt":"2022-07-28T14:00:00","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/oldnewthing\/?p=106912"},"modified":"2022-11-29T10:18:37","modified_gmt":"2022-11-29T18:18:37","slug":"20220728-00-2","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/oldnewthing\/20220728-00\/?p=106912\/","title":{"rendered":"The AArch64 processor (aka arm64), part 3: Addressing modes"},"content":{"rendered":"

Every addressing mode on AArch64 begins with a base register, which can be any numbered register or sp<\/var>. On top of that, you can add various sprinkles.<\/p>\n

In the discussion, the term size<\/var> refers to the size of the data being transferred, and sizeshift<\/var> is the base-2 logarithm of that size:<\/p>\n\n\n\n\n\n\n\n
Operand<\/th>\nsize<\/th>\nsizeshift<\/th>\n<\/tr>\n
byte<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
halfword<\/td>\n2<\/td>\n1<\/td>\n<\/tr>\n
word<\/td>\n4<\/td>\n2<\/td>\n<\/tr>\n
doubleword<\/td>\n8<\/td>\n3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

For illustration purposes, I’ll use the LDR<\/code> instruction, which loads a register.<\/p>\n

Register indirect with offset<\/b><\/p>\n

    ldr     x0, [Xn\/sp, #imm]\r\n    ldr     x0, [Xn\/sp]         ; #0 is implied if omitted\r\n<\/pre>\n
This loads a value from the address calculated by adding the immediate to the value in the Xn<\/var> register or sp<\/var>.<\/p>\n
The immediate can be a signed integer offset in the range \u2212256 to +255, or an unsigned multiple of the operand size up to 4095 \u00d7 size<\/var>.<\/p>\n\n\n\n\n\n\n\n
Size<\/th>\nSigned reach<\/th>\nUnsigned reach<\/th>\n<\/tr>\n
byte<\/td>\n\u2212256 to +255<\/td>\n0 to \u20074095<\/td>\n<\/tr>\n
halfword<\/td>\n0 to \u20078190<\/td>\n<\/tr>\n
word<\/td>\n0 to 16380<\/td>\n<\/tr>\n
doubleword<\/td>\n0 to 32760<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
Register indirect with pre-increment<\/b><\/p>\n
Putting an exclamation point after the close-bracket means that the calculated effective address is written back to the base register.<\/p>\n
    ; load from (Xn\/sp + imm)\r\n    ; then set Xn\/sp = Xn\/sp + imm\r\n    ldr     x0, [Xn\/sp, #imm]!\r\n<\/pre>\n
Register indirect with post-increment<\/b><\/p>\n
Putting the immediate offset outside the close-bracket means that the base register is adjusted after<\/i> the memory is read.<\/p>\n
    ; load from Xn\/sp\r\n    ; then set Xn\/sp = Xn\/sp + imm\r\n    ldr     x0, [Xn\/sp], #imm\r\n<\/pre>\n
PC-relative with offset<\/b><\/p>\n
    ldr     x0, [pc, #imm]\r\n<\/pre>\n
The PC-relative addressing mode reads memory from a position given as a signed offset from the current instruction. The offset must be a multiple of 4, and the reach is \u00b11MB.<\/p>\n
This instruction is typically used to load large constants from memory, and the disassembler does the math for you and decodes it as<\/p>\n
    ldr     x0, =imm\r\n<\/pre>\n
by calculating the effective address and fetching the value from that location.<\/p>\n
The assembler typically generates literals into the code segment between subroutines, and the large reach of this instruction means that the need to dump literals prematurely is largely a thing of the past. (By comparison, AArch32’s PC-relative addressing mode had a reach of only \u00b14KB, so it was not uncommon to dump literals in the middle of a function.)<\/p>\n
Register indirect with index<\/b><\/p>\n
    ldr     x0, [Xn\/sp, Rn\/zr, extend]\r\n<\/pre>\n
This addressing mode takes the Rn\/zr<\/var>, transforms it according to the extended register operation extend<\/i>, and adds the result to the Xn\/sp<\/var> register to form the final address.<\/p>\n
For memory access, the following extended register operations are available:<\/p>\n
    \n
  • UXTW<\/code><\/li>\n
  • UXTX<\/code> (aka LSL<\/code>)<\/li>\n
  • SXTW<\/code><\/li>\n
  • SXTX<\/code><\/li>\n<\/ul>\n
    The only acceptable shifts are zero and sizeshift<\/var>. This means that the index register can be treated either as a byte offset or as an element index, where the element is the size of the operand. For example, if you are loading a halfword, then the index register is either a byte offset of a halfword index.<\/p>\n
    Writing out all the possibilities produces these possible extended registers:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n
    Extended<\/th>\nEffective address<\/th>\nIndex format<\/th>\n<\/tr>\n
    [a, b, UXTW #0]<\/code>
    \n[a, b, UXTW]<\/code><\/td>\n    		a + (uint32_t)b<\/code><\/td>\n32-bit<\/td>\nunsigned<\/td>\nbyte offset.<\/td>\n<\/tr>\n
    [a, b, UXTW #sizeshift]<\/code><\/td>\na + (uint32_t)b * size<\/code><\/td>\n32-bit<\/td>\nunsigned<\/td>\nelement offset.<\/td>\n<\/tr>\n
    [a, b, SXTW #0]<\/code>
    \n[a, b, SXTW]<\/code><\/td>\n    		a + \u00a0(int32_t)b<\/code><\/td>\n32-bit<\/td>\nsigned<\/td>\nbyte offset.<\/td>\n<\/tr>\n
    [a, b, SXTW #sizeshift]<\/code><\/td>\na + \u00a0(int32_t)b * size<\/code><\/td>\n32-bit<\/td>\nsigned<\/td>\nelement offset.<\/td>\n<\/tr>\n
    [a, b, UXTX #0]<\/code>
    \n[a, b, UXTX]<\/code>
    \n[a, b, LSL #0]<\/code>
    \n[a, b]<\/code><\/td>\n    		a + (uint64_t)b<\/code><\/td>\n64-bit<\/td>\nunsigned<\/td>\nbyte offset.<\/td>\n<\/tr>\n
    [a, b, UXTX #sizeshift]<\/code>
    \n[a, b, LSL #sizeshift]<\/code><\/td>\n    		a + (uint64_t)b * size<\/code><\/td>\n64-bit<\/td>\nunsigned<\/td>\nelement offset.<\/td>\n<\/tr>\n
    [a, b, SXTX #0]<\/code><\/td>\na + \u00a0(int64_t)b<\/code><\/td>\n64-bit<\/td>\nsigned<\/td>\nbyte offset.<\/td>\n<\/tr>\n
    [a, b, SXTX #sizeshift]<\/code><\/td>\na + \u00a0(int64_t)b * size<\/code><\/td>\n64-bit<\/td>\nsigned<\/td>\nelement offset.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
    If no extended operation is provided, it defaults to UXTX #0<\/code>, which means “use the whole register, no shift.”<\/p>\n
    There is no pre-increment or post-increment option for the indexed addressing modes.<\/p>\n
    Okay, so those are the addressing modes. Quite a lot to choose from. Next time, we’ll start doing arithmetic.<\/p>\n","protected":false},"excerpt":{"rendered":"
    The ways of accessing memory.<\/p>\n","protected":false},"author":1069,"featured_media":111744,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[2],"class_list":["post-106912","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-oldnewthing","tag-history"],"acf":[],"blog_post_summary":"
    The ways of accessing memory.<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/106912","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/users\/1069"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/comments?post=106912"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/posts\/106912\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media\/111744"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/media?parent=106912"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/categories?post=106912"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/oldnewthing\/wp-json\/wp\/v2\/tags?post=106912"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}