Okay, we’re ready to do some arithmetic. Due to the limited instruction encoding space, there isn’t room for any three-operand instructions.\u00b9 All of the arithmetic instructions are two-operand, where the second source operand also acts as the destination.<\/p>\n
ADD Rm, Rn ; Rn += Rm , no effect on T\r\n ADD #imm, Rn ; Rn += imm , no effect on T\r\n ADDC Rm, Rn ; Rn += Rm + T, T receives carry\r\n ADDV Rm, Rn ; Rn += Rm , T receives signed overflow\r\n<\/pre>\nThe
ADD<\/code> instructions add two values and put the result in the second register. You can add two registers together, or you can add a signed 8-bit immediate to the destination register.<\/p>\nThe
ADDC<\/code> instruction treats the T<\/var> flag as a carry flag: It is added to the sum, and it receives the carry of the result.<\/p>\nThe
ADDV<\/code> instruction treats the T<\/var> flag as an overflow flag: It reports whether a signed overflow occurred.<\/p>\nOkay, subtraction is going to look really similar now.<\/p>\n
SUB Rm, Rn ; Rn -= Rm , no effect on T\r\n SUB #imm, Rn ; Rn -= imm , no effect on T\r\n SUBC Rm, Rn ; Rn -= Rm + T, T receives borrow\r\n SUBV Rm, Rn ; Rn -= Rm , T receives signed underflow\r\n<\/pre>\nBasically the same as addition, except you’re now subtracting. The SH-3 treats T<\/var> as a borrow flag in the case of
SUBC<\/code>, whereas forSUBV<\/code> it reports whether a signed underflow occurred.<\/p>\nArithmetic negation is up next.<\/p>\n
NEG Rm, Rn ; Rn = -Rm , no effect on T\r\n NEGC Rm, Rn ; Rn = -Rm - T, T receives borrow\r\n<\/pre>\nThere is no
NEGV<\/code>, but overflow occurs only if the value is0x80000000<\/code>, so I guess you could test for that value specifically.<\/p>\nThere is a special instruction for for decrementing a register:<\/p>\n
DT Rn ; Rn = Rn - 1, T = (Rn == 0)\r\n<\/pre>\nThe decrement and test<\/i> instruction decrements a register and compares the result against zero. This is presumably for counted loops.<\/p>\n
Next come the comparison instructions.<\/p>\n
CMP\/EQ #imm, r0 ; T = (r0 == signed 8-bit immediate)\r\n CMP\/EQ Rm, Rn ; T = (Rn == Rm)\r\n CMP\/HS Rm, Rn ; T = (Rn \u2265 Rm), unsigned comparison\r\n CMP\/GE Rm, Rn ; T = (Rn \u2265 Rm), signed comparison\r\n CMP\/HI Rm, Rn ; T = (Rn > Rm), unsigned comparison\r\n CMP\/GT Rm, Rn ; T = (Rn > Rm), signed comparison\r\n CMP\/PZ Rn ; T = (Rn \u2265 0), signed comparison\r\n CMP\/PL Rn ; T = (Rn > 0), signed comparison\r\n CMP\/STR Rm, Rn ; T = 1 iff any corresponding bytes are equal\r\n<\/pre>\nThese instructions set the T<\/var> flag according to a particular comparison. Note that the comparison is backward! For example,
CMP\/GE r1, r2<\/code> does not check whether r1<\/var>\u00a0\u2265\u00a0r2<\/var>; rather, it checks whether r2<\/var>\u00a0\u2265\u00a0r1<\/var>. This takes a lot of getting used to.<\/i><\/p>\nYou have the special ability to compare r0<\/var> for equality with a signed 8-bit immediate. Otherwise, you can compare two registers against each other, or a register against zero.<\/p>\n
The special
CMP\/STR<\/code> compares two registers to determine whether any of the four component bytes are equal. It’s clear from the mnemonic that the intended purpose is to search for a null terminator in a string. You set Rn<\/var> to zero and then do aCMP\/STR<\/code> against every longword in the string until it says, “Hey, I found a zero byte!” and then you can study that longword to see where the zero byte is.<\/p>\nThe processor documentation doesn’t explain why they chose the names for the mnemonics, but I can guess.<\/p>\n
\n\n
\n Condition<\/th>\n Meaning<\/th>\n<\/tr>\n \n EQ<\/code><\/td>\nequal<\/td>\n<\/tr>\n \n HS<\/code><\/td>\nhigh or same<\/td>\n<\/tr>\n \n GE<\/code><\/td>\ngreater or equal<\/td>\n<\/tr>\n \n HI<\/code><\/td>\nhigh<\/td>\n<\/tr>\n \n GT<\/code><\/td>\ngreater than<\/td>\n<\/tr>\n \n PZ<\/code><\/td>\nplus or zero<\/td>\n<\/tr>\n \n PL<\/code><\/td>\nplus<\/td>\n<\/tr>\n \n STR<\/code><\/td>\nstring<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n It took me a while to come up with a plausible explanation for
HS<\/code>.<\/p>\nExercise 1<\/b>: Synthesize the
SETT<\/code> andCLRT<\/code> instructions.<\/p>\nExercise 2<\/b>: Perform the opposite of the
MOVT<\/code> instruction: Set the T<\/var> register to 0 if a register is zero, or 1 if the register is nonzero.<\/p>\nThe last arithmetic instructions are the extension instructions.<\/p>\n
EXTS.B Rm, Rn ; sign extend byte in Rm to Rn\r\n EXTS.W Rm, Rn ; sign extend word in Rm to Rn\r\n EXTU.B Rm, Rn ; zero extend byte in Rm to Rn\r\n EXTU.W Rm, Rn ; zero extend word in Rm to Rn\r\n<\/pre>\n