{"id":13389,"date":"2026-04-27T10:01:04","date_gmt":"2026-04-27T17:01:04","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/directx\/?p=13389"},"modified":"2026-04-27T10:13:07","modified_gmt":"2026-04-27T17:13:07","slug":"shader-model-6-10-agilitysdk-720-preview","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/directx\/shader-model-6-10-agilitysdk-720-preview\/","title":{"rendered":"Announcing Shader Model 6.10 Preview and AgilitySDK 720 Preview"},"content":{"rendered":"<h2 style=\"text-align: left;\">Overview<\/h2>\n<hr \/>\n<p style=\"text-align: left;\">Today, we are pleased to announce that Shader Model 6.10 and other features have been officially released with Agility SDK 1.720-preview and complementary DXC 1.10.2605.2.<strong> AgilitySDK 1.720-preview<\/strong> exposes the following features. There&#8217;s more detail further below, including download and driver links.<\/p>\n<ul style=\"text-align: left;\">\n<li>Shader Model 6.10 (via DXC 1.10.2605.2):\n<ul style=\"text-align: left;\">\n<li>linalg::Matrix<\/li>\n<li>Group Wave Index<\/li>\n<li>Variable Group Shared Memory<\/li>\n<li>Raytracing intrinsics\n<ul style=\"text-align: left;\">\n<li>TriangleObjectPositions<\/li>\n<li>ClusterID<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<li>Batched Asynchronous Command List APIs<\/li>\n<\/ul>\n<h3>Downloads<\/h3>\n<ul style=\"text-align: left;\">\n<li>AgilitySDK 1.720-preview: <a href=\"https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/\">https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/<\/a><\/li>\n<li style=\"text-align: left;\">DXC 1.10.2605.2: <a href=\"https:\/\/github.com\/microsoft\/DirectXShaderCompiler\/releases\">https:\/\/github.com\/microsoft\/DirectXShaderCompiler\/releases<\/a><\/li>\n<\/ul>\n<h3>Hardware Support<\/h3>\n<table style=\"width: 99.1509%; height: 96px;\">\n<tbody>\n<tr style=\"height: 24px;\">\n<td style=\"width: 12.7753%; height: 24px;\" width=\"145\"><strong>IHV<\/strong><\/td>\n<td style=\"width: 138.228%; height: 24px;\" width=\"479\"><strong>Driver Link(s)<\/strong><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 12.7753%; height: 24px;\" width=\"145\">AMD<\/td>\n<td style=\"width: 138.228%; height: 24px;\" width=\"479\"><a class=\"Hyperlink SCXW143469361 BCX8\" href=\"https:\/\/www.amd.com\/en\/resources\/support-articles\/release-notes\/RN-RAD-MS-AGILITY-SDK-25-30-41-02.html\" target=\"_blank\" rel=\"noreferrer noopener\"><span class=\"TextRun Underlined SCXW143469361 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"none\"><span class=\"NormalTextRun SCXW143469361 BCX8\" data-ccp-charstyle=\"Hyperlink\">AMD Software:\u00a0<\/span><span class=\"NormalTextRun SCXW143469361 BCX8\" data-ccp-charstyle=\"Hyperlink\">AgilitySDK<\/span><span class=\"NormalTextRun SCXW143469361 BCX8\" data-ccp-charstyle=\"Hyperlink\">\u00a0Developer Preview Edition 25.30.41<\/span><span class=\"NormalTextRun SCXW143469361 BCX8\" data-ccp-charstyle=\"Hyperlink\">.02<\/span><\/span><\/a><span class=\"EOP Selected SCXW143469361 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 12.7753%; height: 24px;\" width=\"145\">Intel<\/td>\n<td style=\"width: 138.228%; height: 24px;\" width=\"479\"><a class=\"Hyperlink SCXW78617547 BCX8\" href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/download\/785597\/918135\/intel-arc-graphics-windows.html\" target=\"_blank\" rel=\"noreferrer noopener\"><span class=\"TextRun Underlined SCXW78617547 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"none\"><span class=\"NormalTextRun SCXW78617547 BCX8\" data-ccp-charstyle=\"Hyperlink\">Intel\u00ae Arc\u2122 Graphics &#8211; Windows*<\/span><\/span><\/a><span class=\"EOP Selected SCXW78617547 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 12.7753%; height: 24px;\" width=\"145\">NVIDIA<\/td>\n<td style=\"width: 138.228%; height: 24px;\" width=\"479\"><span data-olk-copy-source=\"MessageBody\">Contact your developer relations representative for in-development driver access.<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>See <em>Appendix &gt; Feature Support<\/em> for the full table of each feature&#8217;s supported hardware.<\/p>\n<h2 style=\"text-align: left;\"><span class=\"TextRun SCXW4956687 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"none\"><span class=\"NormalTextRun SCXW4956687 BCX8\" data-ccp-parastyle=\"heading 1\">Features<\/span><\/span><\/h2>\n<hr \/>\n<h3><em>HLSL Features (Shader Model 6.10):<\/em><\/h3>\n<h4 style=\"text-align: left;\">linalg::Matrix<\/h4>\n<p>Shader Model 6.10 introduces a set of Matrix APIs covering a broad swath of use cases. Collectively the feature is called LinAlg (short for Linear Algebra).<\/p>\n<p>We&#8217;ve written a dedicated a blog post covering the feature in depth <a href=\"https:\/\/devblogs.microsoft.com\/directx\/d3d12-linalg-preview\/\">here<\/a>.<\/p>\n<p>Also see the GDC 2026 blog putting this feature in context of the overall ML story for DirectX <a href=\"https:\/\/devblogs.microsoft.com\/directx\/evolving-directx-for-the-ml-era-on-windows\/\">here<\/a>.<\/p>\n<p>HLSL Spec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0035-linalg-matrix.md\">hlsl-specs\/proposals\/0035-linalg-matrix.md at main \u00b7 microsoft\/hlsl-specs<\/a><\/p>\n<h4>Group Wave Index<\/h4>\n<p>Shader Model 6.10 introduces two new intrinsics, GetGroupWaveIndex() and GetGroupWaveCount(), that give compute, mesh, amplification, and node shaders direct knowledge of wave-level structure within a thread group. GetGroupWaveIndex() returns the current wave&#8217;s index (0 to N-1) and GetGroupWaveCount() returns the total number of waves executing the group. These enable wave-level work specialization and cooperation without relying on unsafe workarounds like dividing SV_GroupIndex by WaveGetLaneCount(), which is not\nguaranteed to be correct across all hardware. A single code path now works portably across all wave sizes.<\/p>\n<p>HLSL Spec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0048-group-wave-index.md\">hlsl-specs\/proposals\/0048-group-wave-index.md at main \u00b7 microsoft\/hlsl-specs<\/a><\/p>\n<h4>Variable Group Shared Memory<\/h4>\n<p>Shader Model 6.10 lifts the longstanding 32 KB (28 KB for mesh shaders) cap on groupshared memory by exposing the actual hardware limit through a new runtime query, MaxGroupSharedMemoryPerGroup. Shader authors can use a new [GroupSharedLimit(&lt;bytes&gt;)] entry-point attribute to declare the maximum shared memory their shader requires, giving the compiler a compile-time portability check while still allowing access to the full capacity of modern GPUs. Shaders that omit the attribute continue to be validated against the legacy\nlimits, so existing code is unaffected. This unlocks algorithms like large tile culling, software rasterization bins, and big matrix workloads that were previously constrained by the spec rather than the hardware.<\/p>\n<p>HLSL Spec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0049-variable-groupshared-memory.md\">hlsl-specs\/proposals\/0049-variable-groupshared-memory.md at main \u00b7 microsoft\/hlsl-specs<\/a><\/p>\n<h4>Raytracing intrinsics<\/h4>\n<p><code>TriangleObjectPositions()<\/code> is an intrinsic that can be called from an Any hit or Closest hit shader or RayQuery to obtain the positions of the vertices for the triangle that has been hit.<\/p>\n<p>Spec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0041-triangle-object-positions.md\">https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0041-triangle-object-positions.md<\/a><\/p>\n<p><code>ClusterID()<\/code> is an intrinsic that can be called from an Any hit or Closest hit shader or RayQuery to return the user defined ID of a cluster.\u00a0 This isn&#8217;t currently useful since clustered geometry support for DXR isn&#8217;t ready yet.<\/p>\n<p>HLSL Spec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0045-clustered-geometry.md\">https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0045-clustered-geometry.md<\/a><\/p>\n<p>D3D12 Raytracing spec with work-in progress clustered geometry design (not shipped yet): <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/Raytracing2.md\">https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/Raytracing2.md<\/a><\/p>\n<p>Once the features in this spec ship (tentatively starting with a preview fall 2026), the <code>ClusterID()<\/code> intrinsic will become useful.<\/p>\n<p>&nbsp;<\/p>\n<h3><em>D3D12 Features:<\/em><\/h3>\n<h4>Batched Asynchronous Command List APIs<\/h4>\n<p>D3D12&#8217;s legacy\u00a0<code>CopyBufferRegion<\/code>,\u00a0<code>ClearUnorderedAccessViewFloat\/Uint<\/code>,\u00a0<code>ResolveSubresource<\/code>, and similar commands all execute strictly in series because the old\u00a0<code>ResourceBarrier<\/code> model has no way to express a dependency between two operations of the same type (e.g. copy-dest to copy-dest). This means the GPU stalls between every sequential copy or clear, even when the operations touch completely independent memory. The Batched Async Commands feature addresses this by introducing new command list methods that remove the implicit serialization contract, allowing the driver and hardware to overlap independent work within a single batch call. Developers opt into explicit synchronization using enhanced barriers only where true data hazards exist &#8211; such as when two copies write to overlapping regions of the same buffer &#8211; and everything else runs concurrently.<\/p>\n<p>The feature also modernizes clears with <code>ClearTextureSubresources<\/code>, which clears textures directly by resource pointer and format &#8211; no RTV, UAV, descriptor heaps, or special resource flags required. This is notably the first D3D12 clear that works on block-compressed formats. Correspondingly, <code>FillBuffers<\/code> adds batched, format-aware or raw-pattern buffer fills with configurable repeat counts, replacing the descriptor gymnastics of UAV clears. In addition, new <code>ClearBoundRenderTargetViews<\/code> and <code>ClearBoundDepthStencilView<\/code> commands further improve ergonomics by operating on currently bound targets, enabling mid-render-pass clears and batch clearing multiple RTVs in a single call.<\/p>\n<h2 style=\"text-align: left;\">PIX<\/h2>\n<hr \/>\n<p style=\"text-align: left;\">PIX supports all features released here. See the PIX release blog: (link isn&#8217;t live yet) <a href=\"https:\/\/devblogs.microsoft.com\/pix\/pix-2604-27004-preview\/\">https:\/\/devblogs.microsoft.com\/pix\/pix-2604-27004-preview\/<\/a><\/p>\n<h2 style=\"text-align: left;\">Appendix<\/h2>\n<hr \/>\n<h4><strong>Feature Support<\/strong><\/h4>\n<p>Using the latest drivers linked in <em>Overview<\/em> &gt; <em>Hardware Support<\/em>:<\/p>\n<table style=\"width: 99.9182%; height: 216px;\">\n<tbody>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\"><strong>AMD<\/strong><\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\"><strong>Intel<\/strong><\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\"><strong>NVIDIA<\/strong><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><b>linAlg::Matrix<\/b><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\"><span class=\"TextRun SCXW56613706 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW56613706 BCX8\">Supported on\u00a0<\/span><span class=\"NormalTextRun SCXW56613706 BCX8\">AMD Radeon\u2122 RX 9000 series graphics products<\/span><span class=\"NormalTextRun SCXW56613706 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW56613706 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\"><span class=\"TextRun SCXW97721372 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW97721372 BCX8\">Planned for an upcoming release.<\/span><\/span><span class=\"EOP Selected SCXW97721372 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\"><span class=\"NormalTextRun SCXW12903581 BCX8\">Supported on a<\/span><span class=\"NormalTextRun SCXW12903581 BCX8\">ll RTX hardware.<\/span><\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Group Wave Index<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\"><span class=\"TextRun SCXW99799009 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW99799009 BCX8\">Supported on AMD Radeon\u2122 RX 7000\u00a0<\/span><span class=\"NormalTextRun SCXW99799009 BCX8\">and 9000 series graphics products<\/span><span class=\"NormalTextRun SCXW99799009 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW99799009 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\"><span class=\"TextRun SCXW18003770 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW18003770 BCX8\">Supported on\u00a0<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Intel\u00ae Arc\u2122 B-<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Series Graphics<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW18003770 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\"><span class=\"TextRun SCXW20022451 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW20022451 BCX8\">Planned for an upcoming release<\/span><span class=\"NormalTextRun SCXW20022451 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW20022451 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Variable Group Shared Memory<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\"><span data-contrast=\"auto\">Supported on AMD Radeon\u2122 RX 7000 and 9000 series graphics products.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">Supports default memory limit size only. Higher size limits are planned for future driver releases.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\"><span class=\"TextRun SCXW18003770 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW18003770 BCX8\">Supported on\u00a0<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Intel\u00ae Arc\u2122 B-<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Series Graphics<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW18003770 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\"><span data-contrast=\"auto\">Supported on all RTX hardware.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">Values differ across hardware.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Raytracing intrinsics: TriangleObjectPositions\/ClusterID<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\"><span data-contrast=\"auto\">Supported on AMD Radeon\u2122 RX 7000 and 9000 series graphics\u00a0products.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\"><span class=\"TextRun SCXW18003770 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW18003770 BCX8\">Supported on\u00a0<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Intel\u00ae Arc\u2122 B-<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Series Graphics<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW18003770 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\"><span class=\"TextRun SCXW190539521 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW190539521 BCX8\">Supported on all<\/span><span class=\"NormalTextRun SCXW190539521 BCX8\">\u00a0RTX hardware.\u00a0<\/span><\/span><span class=\"EOP Selected SCXW190539521 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>Batched Asynchronous Command List APIs<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\"><span class=\"NormalTextRun SCXW48427780 BCX8\">Supported on AMD Radeon\u2122 RX 7000 and 9000 series graphics\u00a0<\/span><span class=\"NormalTextRun SCXW48427780 BCX8\">products.<\/span><\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\"><span class=\"TextRun SCXW18003770 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW18003770 BCX8\">Supported on\u00a0<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Intel\u00ae Arc\u2122 B-<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">Series Graphics<\/span><span class=\"NormalTextRun SCXW18003770 BCX8\">.<\/span><\/span><span class=\"EOP Selected SCXW18003770 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\"><span class=\"TextRun SCXW99856015 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW99856015 BCX8\">Supported on a<\/span><span class=\"NormalTextRun SCXW99856015 BCX8\">ll RTX hardware.\u00a0<\/span><\/span><span class=\"EOP Selected SCXW99856015 BCX8\" data-ccp-props=\"{}\">\u00a0<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Overview Today, we are pleased to announce that Shader Model 6.10 and other features have been officially released with Agility SDK 1.720-preview and complementary DXC 1.10.2605.2. AgilitySDK 1.720-preview exposes the following features. There&#8217;s more detail further below, including download and driver links. Shader Model 6.10 (via DXC 1.10.2605.2): linalg::Matrix Group Wave Index Variable Group Shared [&hellip;]<\/p>\n","protected":false},"author":8584,"featured_media":12651,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[],"class_list":["post-13389","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-directx"],"acf":[],"blog_post_summary":"<p>Overview Today, we are pleased to announce that Shader Model 6.10 and other features have been officially released with Agility SDK 1.720-preview and complementary DXC 1.10.2605.2. AgilitySDK 1.720-preview exposes the following features. There&#8217;s more detail further below, including download and driver links. Shader Model 6.10 (via DXC 1.10.2605.2): linalg::Matrix Group Wave Index Variable Group Shared [&hellip;]<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/13389","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/users\/8584"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/comments?post=13389"}],"version-history":[{"count":6,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/13389\/revisions"}],"predecessor-version":[{"id":13635,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/13389\/revisions\/13635"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/media\/12651"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/media?parent=13389"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/categories?post=13389"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/tags?post=13389"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}