{"id":12769,"date":"2026-02-26T10:05:50","date_gmt":"2026-02-26T18:05:50","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/directx\/?p=12769"},"modified":"2026-02-26T15:52:37","modified_gmt":"2026-02-26T23:52:37","slug":"shader-model-6-9-retail-and-more","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/directx\/shader-model-6-9-retail-and-more\/","title":{"rendered":"Announcing Shader Model 6.9 Retail and New D3D12 Improvements"},"content":{"rendered":"<p style=\"text-align: left;\">Today, we are pleased to announce that Shader Model 6.9 and other features have been officially released with Agility SDK 1.619 and complementary DXC <span data-olk-copy-source=\"MessageBody\">1.9.2602.16<\/span>. Many of these features have been in preview status since 2025. Simultaneously, we are releasing a handful of new preview features in a separate preview runtime: Agility SDK 1.719-preview.<\/p>\n<h2 style=\"text-align: left;\">Overview<\/h2>\n<hr \/>\n<p style=\"text-align: left;\"><strong>AgilitySDK 1.619<\/strong> exposes the following features. There&#8217;s more detail further below, including download and driver links.<\/p>\n<ul style=\"text-align: left;\">\n<li><strong>Shader Model 6.9 (via DXC 1.9.2602.16):<\/strong>\n<ul style=\"text-align: left;\">\n<li>Long Vector<\/li>\n<li>16 bit float Specials<\/li>\n<li>16-bit and 64-bit shader op and wave ops are now required features<\/li>\n<li>HLSL exposure of the following in DXR 1.2:<\/li>\n<\/ul>\n<\/li>\n<li><strong>DXR 1.2:<\/strong>\n<ul>\n<li>Opacity Micromaps (Released earlier, with small SM 6.9 portion lit up now)<\/li>\n<li>Shader Execution Reordering<\/li>\n<\/ul>\n<\/li>\n<li><strong>D3D Customer-Requested Features:<\/strong>\n<ul style=\"text-align: left;\">\n<li>Revised Resource View Creation APIs<\/li>\n<li>Periodic Trim Notifications<\/li>\n<li>Increased Dispatch Grid Limit<\/li>\n<li>CPU Timeline Query Resolves<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p style=\"text-align: left;\"><strong>AgilitySDK 1.719-preview<\/strong> exposes the features in 1.619 in addition to the following preview D3D features, with more detail further below.<\/p>\n<ul style=\"text-align: left;\">\n<li>Enhanced Barriers update: Fence Barriers<\/li>\n<li>VPblit 3DLUT<\/li>\n<li>Extension Mechanism<\/li>\n<\/ul>\n<h3 style=\"text-align: left;\"><span style=\"font-size: 18pt;\">Downloads<\/span><\/h3>\n<ul>\n<li style=\"text-align: left;\">AgilitySDK 1.619 and 1.719-preview: <a href=\"https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/\">https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/<\/a><\/li>\n<li style=\"text-align: left;\">DXC <span data-olk-copy-source=\"MessageBody\">1.9.2602.17<\/span>: <a href=\"https:\/\/github.com\/microsoft\/DirectXShaderCompiler\/releases\">https:\/\/github.com\/microsoft\/DirectXShaderCompiler\/releases<\/a><\/li>\n<\/ul>\n<h3 style=\"text-align: left;\"><span style=\"font-size: 18pt;\">Hardware Support<\/span><\/h3>\n<table style=\"width: 99.1509%;\">\n<tbody>\n<tr>\n<td style=\"width: 12.7753%;\" width=\"145\"><strong>IHV<\/strong><\/td>\n<td style=\"width: 138.228%;\" width=\"479\"><strong>Driver Link(s)<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 12.7753%;\" width=\"145\">AMD<\/td>\n<td style=\"width: 138.228%;\" width=\"479\"><a href=\"https:\/\/nam06.safelinks.protection.outlook.com\/?url=https%3A%2F%2Fwww.amd.com%2Fen%2Fresources%2Fsupport-articles%2Frelease-notes%2FRN-RAD-WIN-26-2-1.html&amp;data=05%7C02%7Cserenatang%40microsoft.com%7C14b8cea183e846bcb24c08de6b37fd53%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C639066085413615092%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&amp;sdata=%2FZJRJM4qS5dffiToO%2BmREk%2FwttpjebymyZz9L%2F3exH0%3D&amp;reserved=0\">AMD Software: Adrenalin Edition 26.2.1<\/a>, <a href=\"https:\/\/nam06.safelinks.protection.outlook.com\/?url=https%3A%2F%2Fwww.amd.com%2Fen%2Fresources%2Fsupport-articles%2Frelease-notes%2FRN-RAD-MS-AGILITY-SDK-25-30-21-01.html&amp;data=05%7C02%7Cserenatang%40microsoft.com%7C14b8cea183e846bcb24c08de6b37fd53%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C639066085413624413%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&amp;sdata=sRwRvXFsckDfBULDF3riGM3dFbCWxp1cjdWejiRQU0Y%3D&amp;reserved=0\">AMD Software: AgilitySDK Developer Preview Edition 25.30.21.01<\/a><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 12.7753%;\" width=\"145\">Intel<\/td>\n<td style=\"width: 138.228%;\" width=\"479\"><a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/download\/785597\/intel-arc-graphics-windows.html\">Intel\u00ae Arc\u2122 Graphics &#8211; Windows<\/a><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 12.7753%;\" width=\"145\">NVIDIA<\/td>\n<td style=\"width: 138.228%;\" width=\"479\"><a href=\"https:\/\/www.nvidia.com\/en-us\/drivers\/\">Download The Official NVIDIA Drivers | NVIDIA<\/a> or the NVIDIA App, which handles automatic driver updates.\nDriver version 595 and newer.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>See <em>Appendix &gt; Feature Support<\/em> for the full table of each feature&#8217;s supported hardware.<\/p>\n<h2 style=\"text-align: left;\"><span class=\"TextRun SCXW4956687 BCX8\" lang=\"EN-US\" xml:lang=\"EN-US\" data-contrast=\"none\"><span class=\"NormalTextRun SpellingErrorV2Themed SCXW4956687 BCX8\" data-ccp-parastyle=\"heading 1\">AgilitySDK<\/span><span class=\"NormalTextRun SCXW4956687 BCX8\" data-ccp-parastyle=\"heading 1\">\u00a01.619 Features<\/span><\/span><\/h2>\n<hr \/>\n<h4 style=\"text-align: left;\">Long Vector<\/h4>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">The ability to load, store, and perform elementwise operations on HLSL vectors longer than\u00a04\u00a0elements\u00a0and up to 1024.\u202f Required as part of Shader Model 6.9.<\/span><span data-ccp-props=\"{}\">\nSpec:\u202f<a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0026-hlsl-long-vector-type.md\">https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0026-hlsl-long-vector-type.md<\/a>\n<\/span><\/p>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">In addition to the above spec, check out this overview:\u00a0<\/span><a href=\"https:\/\/devblogs.microsoft.com\/directx\/hlsl-native-and-long-vectors\/\"><span data-contrast=\"none\">https:\/\/devblogs.microsoft.com\/directx\/hlsl-native-and-long-vectors\/<\/span><\/a><a href=\"https:\/\/devblogs.microsoft.com\/directx\/hlsl-native-and-long-vectors\/\"><span data-contrast=\"none\">.<\/span><\/a><span data-contrast=\"auto\">\u00a0This mentions Cooperative Vector\u00a0benefitting\u00a0from Long Vectors; however, note that Cooperative Vector has been deprecated in favor of a future design unifying matrix-matrix and vector-matrix operations, coming in Shader Model 6.10. See this earlier blog:\u00a0<\/span><a href=\"https:\/\/devblogs.microsoft.com\/directx\/shader-model-6-9-and-the-future-of-cooperative-vector\/\"><span data-contrast=\"none\">https:\/\/devblogs.microsoft.com\/directx\/shader-model-6-9-and-the-future-of-cooperative-vector\/<\/span><\/a><\/p>\n<h4 style=\"text-align: left;\">16 bit float Specials<\/h4>\n<p style=\"text-align: left;\">HLSL <code>IsNan(), IsInf(), IsFinite()<\/code> now also support 16 bit floats. Also newly added <code>IsNormal()<\/code>, including 16 bit support.\nSpec: <a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0038-16bit-isspecialfloat.md\">https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0038-16bit-isspecialfloat.md<\/a><\/p>\n<h4 style=\"text-align: left;\">Previously optional features required in SM 6.9<\/h4>\n<p style=\"text-align: left;\">Spec:\u00a0<a href=\"https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0044-sm69-required-features.md\">https:\/\/github.com\/microsoft\/hlsl-specs\/blob\/main\/proposals\/0044-sm69-required-features.md<\/a><\/p>\n<ul style=\"text-align: left;\">\n<li><code>D3D12_FEATURE_DATA_D3D12_OPTIONS4.Native16BitShaderOpsSupported<\/code><\/li>\n<li><code>D3D12_FEATURE_DATA_D3D12_OPTIONS1.WaveOps<\/code><\/li>\n<li><code>D3D12_FEATURE_DATA_D3D12_OPTIONS1.Int64ShaderOps<\/code><\/li>\n<\/ul>\n<h3>DXR 1.2<\/h3>\n<hr \/>\n<h4 style=\"text-align: left;\">Opacity Micromaps<\/h4>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">Opacity\u00a0Micromaps\u00a0(OMMs) enable hardware to handle alpha tested geometry\u00a0more efficiently\u00a0than relying only on costly AnyHit shader invocations.<\/span> <span data-contrast=\"auto\">The overall feature\u00a0shipped previously\u00a0and just the small HLSL\u00a0portion\u00a0is coming out of preview.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/p>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">Blog with more details\u00a0for OMM overall:\u202f<\/span><a href=\"https:\/\/devblogs.microsoft.com\/directx\/d3d12-opacity-micromaps\/\"><span data-contrast=\"none\">https:\/\/devblogs.microsoft.com\/directx\/d3d12-opacity-micromaps\/<\/span><\/a><\/p>\n<h4 style=\"text-align: left;\">Shader Execution Reordering<\/h4>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">Shader Execution Reordering (SER) enables application shader code to inform hardware on how to find coherency across rays so they can be sorted for\u00a0better\u00a0parallel execution.<\/span><span data-ccp-props=\"{}\">\u00a0<\/span><\/p>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">This feature is coming out of preview now.\u00a0\u00a0The addition since preview is that apps can query if a device actually reorders. <\/span><\/p>\n<p style=\"text-align: left;\"><span data-contrast=\"auto\">See details in the device support section of this blog which covers SER overall: <\/span><a href=\"https:\/\/devblogs.microsoft.com\/directx\/shader-execution-reordering\/\"><span data-contrast=\"none\">https:\/\/devblogs.microsoft.com\/directx\/shader-execution-reordering\/<\/span><\/a><\/p>\n<h3 style=\"text-align: left;\">D3D Customer-Requested Features<\/h3>\n<hr \/>\n<h4 style=\"text-align: left;\">Revised Resource View Creation APIs<\/h4>\n<p style=\"text-align: left;\">As GPU architectures have evolved, the original D3D12 view\u2011creation model has shown limitations, especially around buffer access patterns, descriptor management, and alignment rules. Revised View Creation modernizes this area of the API in response to multiple customer requests.<\/p>\n<p style=\"text-align: left;\">Previously, buffers views were limited to being measured in elements. With this change, they can now be measured using byte offsets and sizes too. In addition, variants of view creation have been added that return <code>HRESULT<\/code> rather than <code>void<\/code> to allow for programmatic error handling, as opposed to relying on the debug layer validation and dealing with a device removal.<\/p>\n<p style=\"text-align: left;\">Spec: <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12RevisedCreateViews.md\">https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12RevisedCreateViews.md<\/a><\/p>\n<h4 style=\"text-align: left;\">Periodic Trim Notifications<\/h4>\n<p style=\"text-align: left;\">Kernel-level trim notifications are now available through D3D12 runtime interfaces, enabling applications to receive notifications when the system should trim residency. No new driver support is required for this feature.<\/p>\n<p style=\"text-align: left;\">Spec: <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12_PeriodicTrimNotifications.md\">https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12_PeriodicTrimNotifications.md<\/a><\/p>\n<h4 style=\"text-align: left;\">Increased 1D Dispatch Limit<\/h4>\n<p style=\"text-align: left;\">Increases the maximum 1-Dimensional Dispatch\/DispatchMesh size (Currently 65535) to a device specific value which is much larger for most recent hardware.<\/p>\n<ul style=\"text-align: left;\">\n<li><code>D3D12_FEATURE_DATA_D3D12_OPTIONS22.Max1DDispatchSize<\/code><\/li>\n<li><code>D3D12_FEATURE_DATA_D3D12_OPTIONS22.Max1DDispatchMeshSize<\/code><\/li>\n<\/ul>\n<p style=\"text-align: left;\">Spec: <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12IncreasedDispatchDimension.md\">https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12IncreasedDispatchDimension.md<\/a><\/p>\n<h4 style=\"text-align: left;\">CPU Timeline Query Resolves<\/h4>\n<p style=\"text-align: left;\">A new kind of Query Heap which can be resolved on the CPU timeline, avoiding unnecessary GPU work and overhead. Introduces <code>ID3D12Device15::CreateQueryHeap1<\/code> along with <code>ID3D12Device15::ResolveQueryData.<\/code><\/p>\n<p style=\"text-align: left;\">Spec: <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12CpuTimelineQueryResolution.md\">https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12CpuTimelineQueryResolution.md<\/a><\/p>\n<h2 style=\"text-align: left;\">AgilitySDK 1.719-preview Features<\/h2>\n<p style=\"text-align: left;\">The following preview features are available in 1.719-preview: <a href=\"https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/\">https:\/\/devblogs.microsoft.com\/directx\/directx12agility\/<\/a><\/p>\n<hr \/>\n<h4 style=\"text-align: left;\">Enhanced Barriers update: Fence Barriers<\/h4>\n<p style=\"text-align: left;\"><span data-teams=\"true\">Fence Barriers expand on Enhanced Barriers to provide support for signaling and waiting on fences\u00a0during\u00a0command buffer execution. This provides more flexibility to synchronize between more distant dependencies in the command stream and allows for real-time dependencies between the GPU timeline and CPU timeline.<\/span><\/p>\n<p style=\"text-align: left;\">See this separate blog for full details: <a href=\"https:\/\/devblogs.microsoft.com\/directx\/fence-barriers-fine-grained-gpu-synchronization-in-direct3d-12\/\">https:\/\/devblogs.microsoft.com\/directx\/fence-barriers-fine-grained-gpu-synchronization-in-direct3d-12\/<\/a><\/p>\n<h4 style=\"text-align: left;\">VPblit 3DLUT<\/h4>\n<p style=\"text-align: left;\">The D3D12 VPBlit 3DLUT API enables access to dedicated video processing hardware for tone mapping operations that combine CSC, 1D LUT, and 3D LUT stages. While equivalent functionality can be achieved using D3D12 shaders on the 3D engine, exposing the video processing 3DLUT path through this API allows drivers and hardware to execute these operations more efficiently. This offloads tone mapping work from the 3D GPU engine and, in some scenarios, can reduce power consumption by leveraging the video processing engine. For detailed information, please refer to <a href=\"https:\/\/github.com\/microsoft\/DirectX-Specs\/blob\/master\/d3d\/D3D12_Video_Processing_LUT.md\">the spec document<\/a>.<\/p>\n<p style=\"text-align: left;\">Driver support is available as follows:<\/p>\n<ul>\n<li style=\"text-align: left;\"><strong>Intel: <\/strong>Intel Core\u2122 Ultra processor family Lunar Lake and Panther Lake platforms have support for this feature when using driver version 32.0.101.8531<strong><span style=\"color: #ff0000;\">\u00a0<\/span><\/strong>or higher<strong>.<\/strong>\u00a0Developers can also refer to <a href=\"https:\/\/github.com\/intel-samples\/D3D12VPBlitLUT\">Intel&#8217;s D3D12 VPBlit 3DLUT sample app<\/a>.<\/li>\n<li style=\"text-align: left;\"><strong>AMD: <\/strong>AMD\u2019s driver will support the 3DLUT API beginning with the Feb 2026 Developer Preview release (25.30) on Radeon\u2122 RX 7000 series graphics cards and Ryzen\u2122 AI 300\/400 series processors with integrated graphics.<\/li>\n<li style=\"text-align: left;\"><strong>Other IHVs<\/strong>: Please contact your developer relations representative for specifics.<\/li>\n<\/ul>\n<h4 style=\"text-align: left;\">Extension Mechanism<\/h4>\n<p style=\"text-align: left;\">The D3D12 Extensions API enables GPU hardware vendors (IHVs) and software developers (ISVs) to collaborate on new experimental graphics features. By providing a structured extension mechanism within the D3D12 ecosystem, vendors can expose experimental or vendor-specific capabilities immediately, gather real-world feedback, and iterate rapidly\u2014dramatically shortening the time it takes to bring features into the core API.<\/p>\n<p style=\"text-align: left;\">The core interface,\u00a0<code>ID3D12Extension<\/code>, derives from\u00a0<code>ID3D12DeviceChild<\/code>\u00a0and integrates seamlessly with D3D12&#8217;s object model. Extensions communicate through\u00a0<code>D3D12_EXTENSION_ARGUMENTS<\/code>\u00a0(flexible input\/output buffers) and can hook into standard operations like resource creation via\u00a0<code>ID3D12DeviceApiExtensions<\/code>.<\/p>\n<h2 style=\"text-align: left;\">PIX<\/h2>\n<hr \/>\n<p style=\"text-align: left;\">PIX supports all retail and preview features released here. See this PIX blog: <a href=\"https:\/\/devblogs.microsoft.com\/pix\/pix-2602-25\">https:\/\/devblogs.microsoft.com\/pix\/pix-2602-25<\/a><\/p>\n<h2 style=\"text-align: left;\">Appendix<\/h2>\n<hr \/>\n<h4><strong>Feature Support<\/strong><\/h4>\n<p>Using the latest drivers linked in <em>Overview<\/em> &gt; <em>Hardware Support<\/em>:<\/p>\n<table style=\"width: 99.9182%; height: 408px;\">\n<tbody>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\"><strong>AMD<\/strong><\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\"><strong>Intel<\/strong><\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\"><strong>NVIDIA<\/strong><\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>Long Vector<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\">AMD Radeon\u2122 RX 9000 series<\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\">All RTX hardware<\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>16 bit float Specials<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\">AMD Radeon\u2122 RX 9000 series<\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\">\u00a0All RTX hardware<\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Opacity Micromaps (OMM)<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\">&#8211;<\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\">&#8211;<\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\">\u00a0All RTX hardware. Hardware-accelerated on RTX 4xxx+ GPUs, software-emulated on older.<\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Shader Execution Reordering (SER)<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\">AMD Radeon\u2122 RX 9000 series supports API but doesn&#8217;t reorder.<\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics support API and do reordering.<\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\">RTX 4xxx+ GPUs support API and do reordering.<\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Revised Resource View Creation APIs<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\">AMD Radeon\u2122 RX 7000 and 9000 series<\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\">\u00a0All RTX hardware<\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>Periodic Trim Notifications<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\">&#8211;<\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\">\u00a0All RTX hardware<\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>Increased Dispatch Grid Limit<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\">AMD Radeon\u2122 RX 7000 and 9000 series.\nUINT_MAX compute, 64k mesh.<\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics.\nExisting 64k limit, to increase in future drivers.<\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\">All RTX hardware.\nExisting 64k limit, to increase in future drivers.<\/td>\n<\/tr>\n<tr style=\"height: 24px;\">\n<td style=\"width: 19.755%; height: 24px;\" width=\"125\"><strong>CPU Timeline Query Resolves<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 24px;\" width=\"163\">AMD Radeon\u2122 RX 7000 and 9000 series<\/td>\n<td style=\"width: 25.7274%; height: 24px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 24px;\" width=\"172\">\u00a0All RTX hardware<\/td>\n<\/tr>\n<tr style=\"height: 48px;\">\n<td style=\"width: 19.755%; height: 48px;\" width=\"125\"><strong>Fence Barriers (preview)<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 48px;\" width=\"163\">AMD Radeon\u2122 RX 7000 and 9000 series<\/td>\n<td style=\"width: 25.7274%; height: 48px;\" width=\"164\">Intel\u00ae Arc\u2122 B-Series Graphics<\/td>\n<td style=\"width: 78.073%; height: 48px;\" width=\"172\">Contact your developer relations representative for in-development driver access.<\/td>\n<\/tr>\n<tr style=\"height: 72px;\">\n<td style=\"width: 19.755%; height: 72px;\" width=\"125\"><strong>VPblit 3DLUT (preview)<\/strong><\/td>\n<td style=\"width: 25.5743%; height: 72px;\" width=\"163\">AMD Radeon\u2122 RX 7000 series graphics cards and Ryzen\u2122 AI 300\/400 series processors with integrated graphics<\/td>\n<td style=\"width: 25.7274%; height: 72px;\" width=\"164\">Intel Core\u2122 Ultra processor family Lunar Lake and Panther Lake platforms<\/td>\n<td style=\"width: 78.073%; height: 72px;\" width=\"172\">Contact your developer relations representative for specifics.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Today, we are pleased to announce that Shader Model 6.9 and other features have been officially released with Agility SDK 1.619 and complementary DXC 1.9.2602.16. Many of these features have been in preview status since 2025. Simultaneously, we are releasing a handful of new preview features in a separate preview runtime: Agility SDK 1.719-preview. Overview [&hellip;]<\/p>\n","protected":false},"author":8584,"featured_media":12651,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[],"class_list":["post-12769","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-directx"],"acf":[],"blog_post_summary":"<p>Today, we are pleased to announce that Shader Model 6.9 and other features have been officially released with Agility SDK 1.619 and complementary DXC 1.9.2602.16. Many of these features have been in preview status since 2025. Simultaneously, we are releasing a handful of new preview features in a separate preview runtime: Agility SDK 1.719-preview. Overview [&hellip;]<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/12769","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/users\/8584"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/comments?post=12769"}],"version-history":[{"count":5,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/12769\/revisions"}],"predecessor-version":[{"id":13074,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/posts\/12769\/revisions\/13074"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/media\/12651"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/media?parent=12769"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/categories?post=12769"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/directx\/wp-json\/wp\/v2\/tags?post=12769"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}