{"id":783,"date":"2014-02-28T14:30:00","date_gmt":"2014-02-28T14:30:00","guid":{"rendered":"https:\/\/blogs.msdn.microsoft.com\/vcblog\/2014\/02\/28\/avx2-support-in-visual-studio-c-compiler\/"},"modified":"2021-10-04T17:36:07","modified_gmt":"2021-10-04T17:36:07","slug":"avx2-support-in-visual-studio-c-compiler","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/cppblog\/avx2-support-in-visual-studio-c-compiler\/","title":{"rendered":"AVX2 Support in Visual Studio C++ Compiler"},"content":{"rendered":"

AVX2 is yet another extension to the venerable x86 line of processors, doubling the width of its SIMD vector registers to 256 bits, and adding dozens of new instructions<\/a>.  AVX2 shipped with Intel’s latest processor micro-architecture, codenamed “Haswell<\/a>“.  (Its official name is “4th generation Intel® Core™ processor family”).  As well as AVX2, Haswell supports other features to help make your code run faster:  FMA (Fused Multiply Add) and BMI (Bit Manipulation Instructions), in particular.  Haswell chips appear in many of the latest PCs, laptops and tablets (including our own Surface Pro 2).<\/p>\n

This extra silicon opens a new corner of the playing field for compiler-writers – to take your C++ source and generate these new instructions, making your code run faster than before.  And so we are releasing our initial support for AVX2 with the CTP2 of Visual Studio Update.<\/p>\n

How do you tell the VC++ compiler to generate AVX2 instruction?  From the command line, include the \/arch:AVX2 switch.  If you work within Visual Studio, the screenshot below shows how to set this option.   <\/p>\n

 \"Image<\/a><\/p>\n

Yes, we will add an option to enable AVX2 in the drop-down menu at: Project Property Pages | Configuration Properties | C\/C++ | Code Generation | Enable Enhanced Instruction Set<\/span>.  Likewise, we will add brief help to the command line usage for cl \/? <\/span><\/p>\n

Further points worth calling out on AVX2 support:<\/p>\n

The compiler will generate code that includes AVX2 and FMA instructions.  The resulting binaries will only run on PCs that support these instructions.  If you run the binaries on an older PC, the program will crash, and display a popup like this:<\/p>\n

\"Image<\/a><\/p>\n

If you specify \/arch:AVX2<\/span>, then it also enables \/arch:AVX<\/span> – we try to keep those \/arch<\/span> switches ‘monotonic’:  the capabilities of each switch in the sequence {IA32, SSE, SSE2, AVX, AVX2}<\/span> subsumes its predecessor (not sure I’ve explained this well – is it clear?)<\/p>\n

The AVX2 support in this CTP is just a start.  We have more work to do!  This really should not come as a surprise – in a sense, compiler optimizations are never “finished”.  Compiler engineers have been improving optimizations since they were started in the mid-50s by John Backus in the FORTRAN I project.  But it’s worth emphasizing, if only to fend off a little flurry of advice saying we could improve parts of our AVX2 codegen \ud83d\ude42<\/p>\n

If you want to write code that checks for whether the machine you are running is “Haswell-capable”, then you need to check 5 configuration bits, via the CPUID instruction. This Intel page <\/a>explains the details. <\/p>\n

As always, we are interested in your feedback. Post your comments below. Thanks!<\/p>\n

 <\/p>\n

 <\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

AVX2 is yet another extension to the venerable x86 line of processors, doubling the width of its SIMD vector registers to 256 bits, and adding dozens of new instructions.  AVX2 shipped with Intel’s latest processor micro-architecture, codenamed “Haswell“.  (Its official name is “4th generation Intel® Core™ processor family”).  As well as AVX2, Haswell supports other features to help make your […]<\/p>\n","protected":false},"author":271,"featured_media":35994,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[1],"tags":[65],"class_list":["post-783","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-cplusplus","tag-compiler"],"acf":[],"blog_post_summary":"

AVX2 is yet another extension to the venerable x86 line of processors, doubling the width of its SIMD vector registers to 256 bits, and adding dozens of new instructions.  AVX2 shipped with Intel’s latest processor micro-architecture, codenamed “Haswell“.  (Its official name is “4th generation Intel® Core™ processor family”).  As well as AVX2, Haswell supports other features to help make your […]<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts\/783","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/users\/271"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/comments?post=783"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts\/783\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/media\/35994"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/media?parent=783"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/categories?post=783"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/tags?post=783"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}