{"id":35259,"date":"2025-05-13T10:00:25","date_gmt":"2025-05-13T10:00:25","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/cppblog\/?p=35259"},"modified":"2025-04-23T18:37:36","modified_gmt":"2025-04-23T18:37:36","slug":"introducing-the-forceinterlockedfunctions-switch-for-arm64","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/cppblog\/introducing-the-forceinterlockedfunctions-switch-for-arm64\/","title":{"rendered":"Introducing the \/forceInterlockedFunctions switch for ARM64"},"content":{"rendered":"

In Visual Studio 2022 17.14, we are introducing the \/forceInterlockedFunctions[-]<\/code> switch, which generates and links with out-of-line atomics that select Armv8.1+ Large System Extension (LSE) atomic instructions based on CPU support.<\/p>\n

This switch is on by default for Armv8.0 and off for Armv8.1+. Outlining is necessary in Armv8.0 because this version’s interlocked intrinsics use exclusive instructions\u2014LoadExcl<\/code>\/StoreExcl<\/code>\u2014that do not guarantee forward progress. This can cause performance issues due to intermittent livelocks. See Arm Architecture Reference Manual for A-profile architecture<\/a>, section “B2.17.5 Load-Exclusive and Store-Exclusive instruction usage restrictions” for examples of when the LoadExcl<\/code>\/StoreExcl<\/code> loop may not make forward progress.<\/p>\n

Below is an example of code that was previously generated when using the _InterlockedAdd64<\/code> intrinsic. You can see the ldaxr<\/code> and stlxr<\/code> instructions being used.<\/p>\n\n\n\n\n
Main.cpp<\/td>\nMain.asm snippet<\/td>\n<\/tr>\n
\n
#include <intrin.h>\r\n#include <stdio.h>\r\n#include <Windows.h>\r\n\r\nvoid main() {\r\n    volatile __int64 Addend = 5;\r\n    __int64 Value = 1; _InterlockedAdd64(&Addend, Value);\r\n}<\/code><\/pre>\n<\/td>\n
\n
; _InterlockedAdd64(&Addend, Value);\r\nldr x10,[sp]\r\nadd x9,sp,#8\r\n|$LN3@main|\r\nldaxr x8,[x9]\r\nadd x8,x8,x10\r\nstlxr wip0,x8,[x9]\r\ncbnz wip0,|$LN3@main|\r\ndmb ish<\/code><\/pre>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
With the \/forceInterlockedFunctions<\/code> option you can see that the ldaxr<\/code> and stlxr<\/code> are gone and have been replaced with a bl _InterlockedAdd64<\/code>\u00a0instruction<\/p>\n\n\n\n\n
Main.cpp<\/td>\nMain.asm snippet<\/td>\n<\/tr>\n
\n
#include <intrin.h>\r\n#include <stdio.h>\r\n#include <Windows.h>\r\n\r\nvoid main() {\r\n    volatile __int64 Addend = 5;\r\n    __int64 Value = 1; _InterlockedAdd64(&Addend, Value);\r\n}<\/code><\/pre>\n<\/td>\n
\n
; InterlockedAdd64(&Addend, Value);\r\nldr x1,[sp,#0x10]\r\nadd x0,sp,#0x18\r\nbl _InterlockedAdd64\r\nnop<\/code><\/pre>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
The \/forceInterlockedFunctions<\/code> option only applies to Arm64 and will be ignored if not applicable. Additionally, enabling the LSE feature will override the default outlining behavior in Armv8.0.<\/p>\n
Note that the option is on by default for all Arm64EC versions. We would not recommend turning the option off for ARM64EC, as outlining helps address the memory model differences between Arm64 and x64.<\/p>\n
 <\/p>\n
This flag impacts the following interlocked intrinsics:<\/p>\n
Key:<\/p>\n