{"id":34439,"date":"2024-07-29T19:10:48","date_gmt":"2024-07-29T19:10:48","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/cppblog\/?p=34439"},"modified":"2024-09-10T07:55:15","modified_gmt":"2024-09-10T07:55:15","slug":"msvc-backend-updates-in-visual-studio-2022-version-17-10","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/cppblog\/msvc-backend-updates-in-visual-studio-2022-version-17-10\/","title":{"rendered":"MSVC Backend Updates in Visual Studio 2022 version 17.10"},"content":{"rendered":"<p><a href=\"https:\/\/visualstudio.microsoft.com\/vs\/features\/cplusplus\/\">Visual Studio 2022<\/a> 17.10 brings new optimizations, intrinsics, features, and improvements to the MSVC backend. Check out the highlights below:<\/p>\n<ul>\n<li>Performance improvements and additional functionality for all architectures:\n<ul>\n<li>Improved SLP vectorizer. Now it runs on more functions, recognizes more operations, and may choose to use larger vector widths if allowed by the appropriate <code>\/arch<\/code> flag. Add the <code><a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/qvec-report-auto-vectorizer-reporting-level?view=msvc-170\">\/Qvec-report:1<\/a><\/code> switch and look for info <em>C5003: block vectorized<\/em> for more SLP vectorization.<\/li>\n<li>Support <code>__declspec(guard(overflow))<\/code> with signed operations for add\/mul.<\/li>\n<li><a href=\"https:\/\/devblogs.microsoft.com\/cppblog\/improvements-in-variable-visibility-when-debugging\/\">Improvements in Variable Visibility when Debugging.<\/a><\/li>\n<li>Enabled code coverage of managed C++ binaries targeting .NET Core.<\/li>\n<li>Increase debug information for symbol removal during <a href=\"https:\/\/devblogs.microsoft.com\/cppblog\/improvements-in-variable-visibility-when-debugging\/\"><code>\/LTCG<\/code>.<\/a><\/li>\n<li>Significant improvements to ASAN code generation, fixing codegen bugs, and reducing false negatives. ASAN now emits more checks in the presence of inlining.<\/li>\n<li>Made security improvements to the PDB handling code.<\/li>\n<\/ul>\n<\/li>\n<li>New functionality and performance improvements on ARM64:\n<ul>\n<li>The new <a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/feature-arm64?view=msvc-170\"><code>\/feature<\/code> (ARM64)<\/a> flag allows you to enable one or more optional Arm A-Profile architecture features for a specified ARM64 extension. You can also enable ARM64 features by specifying them in the updated <a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/arch-arm64?view=msvc-170\"><code>\/arch<\/code><\/a>\u00a0ARM64 option. For example, if you\u2019d like to enable feature <code>FEAT_LSE<\/code> (Large System Extensions), you can use both <code>\/feature:lse<\/code> and <code>\/arch:armv8.0<\/code> or only use <code>\/arch:armv8.0+lse<\/code>. Note that only certain ARM64 features are currently supported by MSVC. Along with adding the option to enable Arm A-Profile architecture features, the <code>\/arch<\/code> ARM64 option now has the additional arguments for Armv8-A architecture extension version armv8.9 and Armv9-A architecture extensions armv9.0, armv9.1, armv9.2, armv9.3, and armv9.4. For more information about both options, please refer to our documentation for <a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/arch-arm64?view=msvc-170\"><code>\/feature<\/code> (ARM64)<\/a> and <a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/arch-arm64?view=msvc-170\"><code>\/arch<\/code> (ARM64)<\/a>.<\/li>\n<li>Added Arm64 intrinsics, and variants, for exclusive load\/store and load\/store for unprivileged registers, <code>ldtr<\/code> and <code>sttr<\/code><em>.<\/em> Thanks to our friends at ARM.<\/li>\n<li>Optimized Arm64 CRT functions to run faster and take less space\n<ul>\n<li><code>strstr<\/code>\/<code>wcschr<\/code>\/<code>wcsrchr<\/code>\/<code>wcsstr<\/code><\/li>\n<li><code>strchr<\/code><em>, <\/em><code>strrchr<\/code>, and <code>memchr<\/code>, thanks to our friends at ARM.<\/li>\n<\/ul>\n<\/li>\n<li>Speed up intrinsic expansion by reducing intermediate steps<\/li>\n<li>Support SVE2 instructions in the assembler and disassembler, thanks to our friends at ARM.\n<ul>\n<li>bit permutation<\/li>\n<li>element move and broadcasting<\/li>\n<li>constructive multiplication<\/li>\n<li>polynomial and complex integer arithmetic\/dot product\/matrix multiplication\/comparison<\/li>\n<li>uniform\/widening\/narrowing\/unary DSP operations<\/li>\n<li>cryptography support<\/li>\n<li>extended table lookup<\/li>\n<li>non-temporal gather\/scatter<\/li>\n<li>floating-point extra conversion and floating-point widening multiply-accumulate<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<li>Improvements to ARM64EC:\n<ul>\n<li>No longer generate mismatched thunks with different call signatures<\/li>\n<li>Now considers x64 functions during long-branch optimizations <a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/opt-optimizations?view=msvc-170\"><code>\/OPT:LBR<\/code><\/a><\/li>\n<li><code><a href=\"https:\/\/learn.microsoft.com\/en-us\/cpp\/build\/reference\/map-generate-mapfile?view=msvc-170\">\/map<\/a><\/code> now contains Arm64 native symbols<\/li>\n<\/ul>\n<\/li>\n<li>Performance improvements and additional functionality for x86 and x64:\n<ul>\n<li>Vectorizer optimized to run in additional scenarios, thanks to our friends at AMD.<\/li>\n<li>Optimize FMA generation with <code>\/favor:ATOM<\/code>, thanks to our friends at Intel.<\/li>\n<li>New functionality on x64:\n<ul>\n<li>Support the vectorization of the multiplication of 8-bit types for AVX512, thanks to our friends at Intel.<\/li>\n<li>Support AVX2 and AVX512 variable bit shift instructions, thanks to our friends at AMD.<\/li>\n<li>Our friends at Intel added intrinsics for Intel Lion Cove to enable:\n<ul>\n<li>AVX-VNNI-INT16\n<ul>\n<li><code>VPDPW[SU,US,UU]D[,S]<\/code><\/li>\n<\/ul>\n<\/li>\n<li>TSE\n<ul>\n<li><code>PBNDKB<\/code><\/li>\n<\/ul>\n<\/li>\n<li>SHA512\n<ul>\n<li><code>VSHA512MSG1<\/code><em>, <\/em><code>VSHA512MSG2<\/code><em>, <\/em><code>VSHA512RNDS2<\/code><\/li>\n<\/ul>\n<\/li>\n<li>SM3\n<ul>\n<li><code>VSM3MSG1<\/code><em>, <\/em><code>VMS3MSG2<\/code><em>, <\/em><code>VSM3RNDS2<\/code><\/li>\n<\/ul>\n<\/li>\n<li>SM4\n<ul>\n<li><code>VSM4KEY4<\/code><em>, <\/em><code>VSM4RNDS4<\/code><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>Do you want to experience the new improvements in the C++ backend? Please <a href=\"https:\/\/visualstudio.microsoft.com\/vs\/features\/cplusplus\/\">download the latest Visual Studio 2022<\/a> and give it a try! Any feedback is welcome. We can be reached via the comments below, <a href=\"https:\/\/developercommunity.visualstudio.com\/cpp\">Developer Community<\/a>, X (<a href=\"https:\/\/twitter.com\/visualc\">@VisualC<\/a>), or email at <a href=\"mailto:visualcpp@microsoft.com\">visualcpp@microsoft.com<\/a>.<\/p>\n<p>Stay tuned for more information on updates to the latest Visual Studio.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Visual Studio 2022 17.10 brings new optimizations, intrinsics, features, and improvements to the MSVC backend. Check out the highlights below: Performance improvements and additional functionality for all architectures: Improved SLP vectorizer. Now it runs on more functions, recognizes more operations, and may choose to use larger vector widths if allowed by the appropriate \/arch flag. [&hellip;]<\/p>\n","protected":false},"author":165862,"featured_media":35994,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[3946,1],"tags":[],"class_list":["post-34439","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-backend","category-cplusplus"],"acf":[],"blog_post_summary":"<p>Visual Studio 2022 17.10 brings new optimizations, intrinsics, features, and improvements to the MSVC backend. Check out the highlights below: Performance improvements and additional functionality for all architectures: Improved SLP vectorizer. Now it runs on more functions, recognizes more operations, and may choose to use larger vector widths if allowed by the appropriate \/arch flag. [&hellip;]<\/p>\n","_links":{"self":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts\/34439","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/users\/165862"}],"replies":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/comments?post=34439"}],"version-history":[{"count":0,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/posts\/34439\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/media\/35994"}],"wp:attachment":[{"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/media?parent=34439"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/categories?post=34439"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/devblogs.microsoft.com\/cppblog\/wp-json\/wp\/v2\/tags?post=34439"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}