{"id":25584,"date":"2020-02-27T14:40:13","date_gmt":"2020-02-27T14:40:13","guid":{"rendered":"https:\/\/devblogs.microsoft.com\/cppblog\/?p=25584"},"modified":"2020-02-27T14:40:13","modified_gmt":"2020-02-27T14:40:13","slug":"avx-512-auto-vectorization-in-msvc","status":"publish","type":"post","link":"https:\/\/devblogs.microsoft.com\/cppblog\/avx-512-auto-vectorization-in-msvc\/","title":{"rendered":"AVX-512 Auto-Vectorization in MSVC"},"content":{"rendered":"

In Visual Studio 2019 version 16.3<\/a> we added AVX-512 support to the auto-vectorizer of the MSVC compiler. This post will show some examples and help you enable it in your projects.<\/p>\n

What is the auto vectorizer?<\/h3>\n

The compiler\u2019s auto vectorizer<\/a> analyzes loops in the user\u2019s source code and generates vectorized code for a vectorization target where feasible and beneficial.<\/p>\n

static const int length = 1024 * 8;\r\nstatic float a[length];\r\nfloat scalarAverage() {\r\n    float sum = 0.0;\r\n    for (uint32_t j = 0; j < _countof(a); ++j) {\r\n        sum += a[j];\r\n    }\r\n\r\n    return sum \/ _countof(a);\r\n}<\/pre>\n
For example, if I build the code above using <\/span>cl.exe \/O2 \/fp:fast \/arch:AVX2<\/strong> targeting AVX2, I get the following assembly. The lines 11-15 are the vectorized loop using ymm registers. The lines 16-21 are to calculate the scalar value <\/span>sum<\/strong> from vector values coming out of the vector loop. Please note the number of iterations of the vector loop is only 1\/8 of the scalar loop, which usually translates to improved performance.<\/span><\/p>\n
?scalarAverage@@YAMXZ (float __cdecl scalarAverage(void)):\r\n00000000: push ebp\r\n00000001: mov ebp,esp\r\n00000003: and esp,0FFFFFFF0h\r\n00000006: sub esp,10h\r\n00000009: xor eax,eax\r\n0000000B: vxorps xmm1,xmm1,xmm1\r\n0000000F: vxorps xmm2,xmm2,xmm2\r\n00000013: nop dword ptr [eax]\r\n00000017: nop word ptr [eax+eax]\r\n00000020: vaddps ymm1,ymm1,ymmword ptr ?a@@3PAMA[eax]\r\n00000028: vaddps ymm2,ymm2,ymmword ptr ?a@@3PAMA[eax+20h]\r\n00000030: add eax,40h\r\n00000033: cmp eax,8000h\r\n00000038: jb 00000020<\/span>\r\n0000003A: vaddps ymm0,ymm2,ymm1\r\n0000003E: vhaddps ymm0,ymm0,ymm0\r\n00000042: vhaddps ymm1,ymm0,ymm0\r\n00000046: vextractf128 xmm0,ymm1,1\r\n0000004C: vaddps xmm0,xmm1,xmm0\r\n00000050: vmovaps xmmword ptr [esp],xmm0<\/span>\r\n00000055: fld dword ptr [esp]\r\n00000058: fmul dword ptr [__real@39000000]\r\n0000005E: vzeroupper\r\n00000061: mov esp,ebp\r\n00000063: pop ebp\r\n00000064: ret<\/pre>\n
What is AVX-512?<\/span><\/h3>\n
AVX-512 is a family of processor extensions introduced by Intel which enhance vectorization<\/a> by extending vectors to 512 bits, doubling the number of vector registers, and introducing element-wise operation masking. You can detect support for AVX-512 using the __isa_available variable, which will be 6 or greater if AVX-512 support is found. This indicates support for the F(Foundational) instructions, as well as instructions from the VL, BW, DQ, and CD extensions which add additional integer vector operations, 128-bit and 256-bit operations with the additional AVX-512 registers and masking, and instructions to detect address conflicts with scatter stores. These are the same instructions that are enabled by \/arch:AVX512<\/a> as described below. These extensions are available on all processors with AVX-512 that Windows officially supports. More information about AVX-512 can be found in the following blog posts that we published before.<\/p>\n